AD8304 0

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a
160 dB Range (100 pA–10 mA)
Logarithmic Converter
AD8304
FEATURES
Optimized for Fiber Optic Photodiode Interfacing
Eight Full Decades of Range
Law Conformance 0.1 dB from 1 nA to 1 mA
Single-Supply Operation (3.0 V–5.5 V)
Complete and Temperature Stable
Accurate Laser-Trimmed Scaling:
Logarithmic Slope of 10 mV/dB (at VLOG pin)
Basic Logarithmic Intercept at 100 pA
Easy Adjustment of Slope and Intercept
Output Bandwidth of 10 MHz, 15 V/
s Slew Rate
1, 2, or 3-Pole Low-Pass Filtering at Output
Miniature 14-Lead Package (TSSOP)
Low Power: ~4.5 mA Quiescent Current (Enabled)
FUNCTIONAL BLOCK DIAGRAM
VPS2
PWDN
VPS1
10
2
12
AD8304
PDB
BIAS
VREF
7
VREF
6
VPDB
~1
0k
0.5V
3
VSUM
I
P
D
INPT
8
VLOG
4
TEMPERATURE
COMPENSATION
5k
9
BFIN
VSUM
5
13
BFNG
APPLICATIONS
High-Accuracy Optical Power Measurement
Wide Range Baseband Log Compression
Versatile Detector for APC Loops
1
VNEG
14
11
VOUT
ACOM
PRODUCT DESCRIPTION
The AD8304 is a monolithic logarithmic detector optimized for
the measurement of low-frequency signal power in fiber optic
systems. It uses an advanced translinear technique to provide an
exceptionally large dynamic range in a versatile and easily used
form. Its wide measurement range and accuracy are achieved
using proprietary design techniques and precise laser trimming.
In most applications only a single positive supply V
P
of 5 V will
be required, but 3.0 V to 5.5 V can be used, and certain appli-
cations benefit from the added use of a negative supply, V
N
.
When using low supply voltages, the log slope is readily altered
to fit the available span. The low quiescent current and chip
disable features facilitate use in battery-operated applications.
The input current I
PD
flows in the collector of an optimally
scaled NPN transistor, connected in a feedback path around a
low-offset JFET amplifier. The current-summing input node
operates at a constant voltage, independent of current, with a
default value of 0.5 V; this may be adjusted over a wide range,
including ground or below, using an optional negative supply.
An adaptive biasing scheme is provided for reducing the dark
current at very low light input levels. The voltage at pin VPDB
applies approximately 0.1 V across the diode for I
PD
= 100 pA,
rising linearly with current to 2.0 V of net bias at I
PD
= 10 mA.
The input pin INPT is flanked by the guard pins VSUM that
track the voltage at the summing node to minimize leakage.
The default value of the logarithmic slope at the output VLOG
is accurately scaled to 10 mV/dB (200 mV/decade). The resis-
tance at this output is laser trimmed to 5 kΩ, allowing the slope
to be lowered by shunting it with an external resistance; the
addition of a capacitor at this pin provides a simple low-pass
filter. The intermediate voltage VLOG is buffered in an output
stage that can swing to within about 100 mV of ground (or V
N
)
and the positive supply, V
P
, and provides a peak current drive
capacity of ± 20 mA. The slope can be increased using the buffer
and a pair of external feedback resistors. An accurate voltage
reference of 2 V is also provided to facilitate the repositioning of
the intercept.
Many operational modes are possible. For example, low-pass
filters of up to three poles may be implemented, to reduce the
output noise at low input currents. The buffer may also serve as a
comparator, with or without hysteresis, using the 2 V reference,
for example, in alarm applications. The incremental bandwidth of
a translinear logarithmic amplifier inherently diminishes for small
input currents. At the 1 nA level, the AD8304’s bandwidth is
about 2 kHz, but this increases in proportion to I
PD
up to a maxi-
mum value of 10 MHz.
The AD8304 is available in a 14-lead TSSOP package and
specified for operation from –40°C to +85°C.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
AD8304–SPECIFICATIONS
(V
P
= 5 V, V
N
= 0 V, T
A
= 25
C, unless otherwise noted.)
Parameters
Conditions
Min
Typ
Max
Unit
INPUT INTERFACE
Pin 4, INPT; Pin 3 and Pin 5, VSUM
Specified Current Range
Flows toward INPT pin
100
pA
10
mA
Input Node Voltage
Internally preset; May Be Altered
0.46
0.5
0.54
V
Temperature Drift
–40°C < T
A
< +85°C
0.02
mV/°C
Input Guard Offset Voltage
V
IN
– V
SUM
–20
+20
mV
PHOTODIODE BIAS
1
Established between Pin 6, V
PDB
, and Pin 4
Minimum Value
I
PD
= 100 pA
70
100
mV
Transresistance
200
mV/mA
LOGARITHMIC OUTPUT
Pin 8, VLOG
Slope
Laser-Trimmed at 25°C
196
200
204
mV/dec
0°C < T
A
< 70°C
194
207
mV/dec
Intercept
Laser-Trimmed at 25°C
60
100
140
pA
0°C < T
A
< 70°C
35
175
pA
Law Conformance Error
10 nA < I
PD
< 1 mA, Peak Error
0.05
0.25
dB
1 nA < I
PD
< 1 mA, Peak Error
0.1
0.7
dB
Maximum Output Voltage
1.6
V
Minimum Output Voltage
Limited by V
N
= 0 V
0.1
V
Output Resistance
Laser-Trimmed at 25°C
4.95
5
5.05
kΩ
REFERENCE OUTPUT
Pin 7, VREF
Voltage WRT Ground
Laser-Trimmed at 25°C
1.98
2
2.02
V
–40°C < T
A
< +85°C
1.92
2.08
V
Output Resistance
2
Ω
OUTPUT BUFFER
Pin 9, BFIN; Pin 13, BFNG; Pin 11, VOUT
Input Offset Voltage
–20
+20
mV
Input Bias Current
Flowing out of Pin 9 or Pin 13
0.4
µ
A
Incremental Input Resistance
35
M
Ω
Output Range
R
L
= 1 k
Ω
to ground
V
P
– 0.1
V
Output Resistance
0.5
Ω
Wideband Noise
2
I
PD
> 1
µ
A (see Typical Performance Characteristics)
1
µ
V/
√
Hz
Small Signal Bandwidth
2
I
PD
> 1
µ
A (see Typical Performance Characteristics)
10
MHz
Slew Rate
0.2 V to 4.8 V output swing
15
V/
µ
s
POWER DOWN INPUT
Pin 2, PWDN
Logic Level, HI State
–40°C < T
A
< +85°C, 2.7 V < V
P
< 5.5V
2
V
Logic Level, LO State
–40°C < T
A
< +85°C, 2.7 V < V
P
< 5.5V
1
V
POWER SUPPLY
Pin 10 and Pin 12, VPS1 and VPS2; Pin 1, VNEG
Positive Supply Voltage
3.0
5
5.5
V
Quiescent Current
4.5
5.3
mA
In Disabled State
60
µA
Negative Supply Voltage
3
0
–5.5
V
NOTES
1
This bias is internally arranged to track the input voltage at
INPT; it is not specified relative to ground.
2
Output Noise and Incremental Bandwidth are functions of Input Current: see Typical Performance Characteristics.
3
Optional
Specifications subject to change without notice.
–2–
REV. 0
AD8304
ABSOLUTE MAXIMUM RATINGS
*
Supply Voltage V
P
– V
N
. . . . . . . . . . . . . . . . . . . . . . . . . . . 8 V
Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . 270 mW
JA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C/W
Maximum Junction Temperature . . . . . . . . . . . . . . . . . 125°C
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . . 300°C
PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic Function
1
VNEG
Optional Negative Supply, V
N
.
This pin is usually grounded; for
details of usage, see Applications section.
2
PWDN
Power Down Control Input. Device is
active when PWDN is taken LOW.
3, 5
VSUM
Guard Pins. Used to shield the INPT
current line.
*
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
4
INPT
Photodiode Current Input. Usually
connected to photodiode anode (the
photo current flows toward INPT).
6
VPDB
Photodiode Biaser Output. May be
connected to photodiode cathode to
provide adaptive bias control.
PIN CONFIGURATION
7
VREF
Voltage Reference Output of 2 V.
8
VLOG
Output of the logarithmic front-end
processor; R
OUT
= 5 kΩ to ground.
VNEG
PWDN
VSUM
INPT
VSUM
VPDB
VREF
1
2
3
14
13
12
11
10
9
8
ACOM
BFNG
VPS1
VOUT
VPS2
BFIN
VLOG
9
BFIN
Buffer Amplifier noninverting input
(high impedance)
AD8304
10
VPS2
Positive Supply, V
P
(3.0 V to 5.5 V)
4
5
6
7
TOP VIEW
(Not to Scale)
11
VOUT
Buffer Output; Low Impedance
12
VPS1
Positive Supply, V
P
(3.0 V to 5.5 V)
13
BFNG
Buffer Amplifier Inverting Input
14
ACOM
Analog Ground
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
AD8304ARU
–40°C to +85°C
Tube, 14-Lead TSSOP
RU-14
AD8304ARU-REEL
13" Tape and Reel
AD8304ARU-REEL7
7" Tape and Reel
AD8304-EVAL
Evaluation Board
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD8304 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–3–
AD8304–Typical Performance Characteristics
(V
P
= 5 V, V
N
= 0 V, T
A
= 25
C, unless otherwise noted.)
1.6
0.510
T
A
= –40
C, +25
C, +85
C
V
N
= –0.5V
T
A
= –40
C, +25
C, +85
C
1.4
0.508
1.2
C
+25
C
+85
C
1.0
0.506
0.8
0.6
0.504
–40
C
+25
C
0.4
+85
C
0.502
0.2
100p
1n
10n
100n
1
10
100
1m
10m
0.500
1n
10n
100n
1
10
100
1m
10m
INPUT – A
INPUT – A
TPC 1. V
LOG
vs. I
PD
TPC 4. V
SUM
vs. I
PD
2.0
2.8
T
A
= –40
C, +25
C, +85
C
V
N
= –0.5V
2.6
T
A
= –40
C, +25
C, +85
C
1.5
1.0
–40
C
2.4
2.2
C
+25
C
+85
0.5
2.0
1.8
C
+25
C
0
+85
C
1.6
–0.5
1.4
–1.0
1.2
1.0
–1.5
0.8
–2.
100p
0.6
1n
10n
100n
1
10
100
1m
10m
0
1
2
3
4
5
6
7
8
9
10
INPUT – A
INPUT – mA
TPC 2. Logarithmic Conformance (Linearity) for V
LOG
TPC 5. V
PDB
vs. I
PD
2.0
2.4
1.25
V
P
= 4.5V, 5.0V, 5.5V
V
N
= –0.1V
T
A
= –40
C, +25
C, +85
C
1.5
2.2
V
P
= 3.0V
1.00
1.0
2.0
0.75
1.8
–40
C
0.50
0.5
4.5V
1.6
0.25
0
5.0V
5.5V
1.4
+25
C
0
–0.5
+85
C
1.2
–0.25
–1.0
1.0
–0.50
–1.5
0.8
–0.75
100p
1n
10n
100n
1
10
100
1m
10m
0.6
100p
1n
10n 100n
1
10
100
1m
10m
–1.00
INPUT – A
INPUT – A
TPC 3. Absolute Deviation from Nominal Speci-
fied Value of V
LOG
TPC 6. Logarithmic Conformance (Linearity) for
V
LOG
(See Figure 6.)
–4–
REV. 0
–40
0
100p
–40
–2.0
AD8304
10
100nA
10
10nA
1
A
10
A
9
0
100
A
1nA
10mA
8
–10
1mA
7
–20
6
–30
5
–40
4
3
–50
2
–60
1
–70
100
1k
10k
100k
1M
10M
100M
0
1n
10n
100n
1
10
100
1m
10m
FREQUENCY – Hz
INPUT CURRENT – A
TPC 7. Small Signal AC Response, I
PD
to V
LOG
(1% Sine Modulation of I
PD
at Frequency)
TPC 10. Total Wideband Noise Voltage at V
LOG
vs. I
PD
100
3
GAIN = 1
, 2
, 2.5
, 5
10kHz
100kHz
0
10
A
V
= 5
A
V
= 1
–3
1
A
V
= 2.5
100Hz
–6
A
V
= 2
1kHz
1MHz
0.1
–9
0.01
1n
10n
100n
1
10
100
1m
10m
–12
100
1k
10k
100k
1M
10M
100M
I
PD
–
A
FREQUENCY – Hz
TPC 8. Spot Noise Spectral Density at V
LOG
vs. I
PD
TPC 11. Small Signal Response of Buffer
100
10
f
C
= 1kHz
1nA
0
10
–10
10nA
1
A
–20
1
100nA
–30
10
A
–40
>100
A
0.1
–50
–60
0.01
100
1k
10k
100k
1M
10M
–70
10
100
1k
10k
100k
FREQUENCY – Hz
FREQUENCY – Hz
TPC 9. Spot Noise Spectral Density at V
LOG
vs. Frequency
TPC 12. Small Signal Response of Buffer
Operating as 2-Pole Filter
REV. 0
–5–
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