AD9882 brief, CD1

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AD9882 — Interface for Flat Panel Displays
Key Features
1024 at 75 Hz
• Midscale clamping for HDTV and
DTV (YPbPr signals)
• Integrated sync processing for composite
sync and sync-on-green applications
• Digital interface is fully compatible with
DVI version 1.0 for FPDs to ensure unsur-
passed image quality and minimal user
adjustments
• 112 MHz operation allows the DVI
receiver to support display resolutions
up to 1280 1024 at 60 Hz
• DVI receiver includes support for HDCP
with encrypted external HDCP device
key storage for maximum security and
the industry’s highest level of compatibility
• Evaluation board with full schematics
and software is available
The AD9882 is a low cost, highly integrated dual interface device for XGA and SXGA displays.
Integrated Dual Interface Solutions for Superior Image Quality
The AD9882 is a high-performance, mixed-signal interface that combines low
system cost and excellent image quality with reliable operation. The design of
the AD9882 is optimized to meet the needs of XGA and SXGA displays with-
out compromising performance.
The AD9882 offers designers the flexibility of an analog interface and a
Digital Visual Interface (DVI) receiver integrated on a single chip. Also included
is support for High-Bandwidth Digital Content Protection (HDCP).
The analog interface contains a 140 MHz triple ADC that supports resolutions
up to SXGA (1280 1024 at 75 Hz) with fully integrated sync processing.
The digital interface contains a DVI version 1.0 compatible receiver and
supports display resolutions up to SXGA (1280 1024 at 60 Hz).
With the inclusion of HDCP, displays may now receive encrypted video
content. The AD9882 allows for authentication of a video receiver, decryption
of encoded data at the receiver, and renewability of the authentication during
transmission as specified by the HDCP version 1.0 protocol.
• Low-cost dual interface technology
assures legacy compatibility while still
being “digital ready” for the future
• Analog interface combines
high-performance triple A/D converters
and low-jitter PLL for the highest image
quality possible
• 140 MSPS conversion rate allows the
analog interface to support display
resolutions up to 1280
Product Specifications
General
100–lead LQFP package
0°C to 70°C temperature range
3.3 V power supply
Three-state CMOS outputs operate from
2.5 V to 3.3 V power supply
5.0 V tolerant digital inputs
AD9882 Block Diagram
REF BYPASS
ANALOG INTERFACE
Ref
R
AIN
CLAMP
A/D
8
R
OUT
Analog Interface
140 MSPS maximum conversion rate
Programmable analog bandwidth
0.5 V to 1.0 V analog input range
Low PLL jitter: 500 pS typical at 140 MSPS
Full sync processing
Midscale clamping
4:2:2 output format mode
G
AIN
CLAMP
A/D
8
G
OUT
B
AIN
CLAMP
A/D
8
B
OUT
SOGIN
HSYNC
FILT
VSYNC
SYNC
PROCESSING AND
CLOCK
GENERATION
DATACK
HSOUT
VSOUT
SOGOUT
8
R
OUT
8
G
OUT
Muxes
8
Digital Interface
DVI 1.0 compatible interface
112 MHz operation
High skew tolerance of 1 full input clock
Sync detect for “hot plugging”
Supports High-Bandwidth Digital Content Protection
SCL
SDA
A
0
SERIAL
REGISTER AND
POWER
MANAGEMENT
B
OUT
DATACK
DIGITAL INTERFACE
R
OUT
HSOUT
VSOUT
8
RX0+
RX0-
RX1+
RX1-
RX2+
RX2-
RXC+
RXC-
R
TERM
DDCSCL
DDCSDA
MCL
SOGOUT
DE
G
OUT
8
Applications
RGB graphics processing
LCD monitors and projectors
Plasma display panels
Scan converters
Microdisplays
Digital TV
8
B
OUT
DVI
RECEIVER
DATACK
DE
Hsync
Vsync
HDCP
MDA
WORLDWIDE HEADQUARTERS
One Technology Way, P.O. Box 9106
Norwood, MA 02062-9106, U.S.A.
Tel: 781 329 4700
(1 800 262 5643, U.S.A. only)
Fax: 781 326 8703
www.analog.com
JAPAN HEADQUARTERS
New Pier Takeshiba
South Tower Building
1-16-1 Kaigan, Minato-ku
Tokyo 105-6891, Japan
Tel: 3 5402 8200
Fax: 3 5402 1063
ANALOG DEVICES GmbH
Am Westpark 1 – 3 D-81373
München, Germany
Tel: 49 89 76903 0
Fax: 49 89 76903 157
SOUTHEAST ASIA HEADQUARTERS
4501 Nat West Tower
Times Square
1 Matheson Street
Causeway Bay, Hong Kong, PRC
Tel: 852 2 506 9336
Fax: 852 2 506 4755
www.analog.com/flatpanel
2002 Analog Devices, Inc. All rights reserved. The Analog Devices
logo is a registered trademark. Other trademarks and registered
trademarks are the property of their respective companies.
Printed in the U.S.A
H02900-1.5-2/02(0)
©
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