ADMC401 a

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a
Single-Chip, DSP-Based
High Performance Motor Controller
ADMC401
FEATURES
26 MIPS Fixed-Point DSP Core
Single Cycle Instruction Execution (38.5 ns)
ADSP-21xx Family Code Compatible
16-Bit Arithmetic and Logic Unit (ALU)
Single Cycle 16-Bit
3
16-Bit Multiply and Accumulate
Into 40-Bit Accumulator (MAC)
32-Bit Shifter (Logical and Arithmetic)
Multifunction Instructions
Single Cycle Context Switch
Zero Overhead Looping
Conditional Instruction Execution
Two Independent Data Address Generators
Memory Configuration
2K
3
24-Bit Internal Program Memory RAM
2K
3
24-Bit Internal Program Memory ROM
1K
3
16-Bit Internal Data Memory RAM
14-Bit Address Bus and 24-Bit Data Bus for External
Memory Expansion
High Resolution Multichannel ADC
12-Bit Pipeline Flash Analog-to-Digital Converter
Eight Dedicated Analog Inputs
Simultaneous Sampling Capability
All Eight Inputs Converted in <2
m
s
4.0 V p-p Input Voltage Range
PWM Synchronized or External Convert Start
Internal or External Voltage Reference
Out-of-Range Detection
Voltage Reference
Internal 2.0 V
6
2.0% Voltage Reference
Three-Phase 16-Bit PWM Generation Unit
Programmable Switching Frequency, Dead Time and
Minimum Pulsewidth
Edge Resolution of 38.5 ns
One or Two Updates per Switching Period
Hardware Polarity Control
Individual Enable/Disable of Each Output
High Frequency Chopping Mode
Dedicated Shutdown Pin (PWMTRIP)
Additional Shutdown Pins in I/O System
High Output Sink and Source Capability (10 mA)
Incremental Encoder Interface Unit
Quadrature Rates to 17.3 MHz
Programmable Filtering of Encoder Inputs
Alternative Frequency and Direction Mode
Two Registration Inputs to Latch Count Value
Optional Hardware Reset of Counter
Single North Marker Mode
Count Error Monitor Function
Dedicated 16-Bit Loop Timer (Periodic Interrupts)
Companion Encoder Event (1/T) Timer
(Continued on Page 14)
FUNCTIONAL BLOCK DIAGRAM
26 MIPS DSP CORE
PM
ROM
2K
MEMORY
MOTOR CONTROL
PERIPHERALS
DATA
ADDRESS
GENERATOR
S
DAG 1 DAG 2
24
PM
RAM
2K
3
PROGRAM
SEQUENCER
3
24
DM
RAM
1K
3
16
WATCH-
DOG
TIMER
POWER-
ON
RESET
INTERRUPT
CONTROLLER
ENCODER
INTERFACE
EVENT
CAPTURE
UNIT
DIGITAL
I/O
UNIT
EXTERNAL
ADDRESS
BUS
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
EXTERNAL
DATA
BUS
PROGRAM MEMORY DATA
DATA MEMORY DATA
ARITHMETIC UNITS
SHIFTER
SERIAL PORTS
INTERVAL
TIMER
2 CHANNEL
AUXILIARY
PWM
8 CHANNEL
12-BIT ADC
PRECISION
VOLTAGE
REFERENCE
16-BIT
PWM
GENERATION
ALU
MAC
SPORT 0
SPORT 1
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
ADMC401–SPECIFICATIONS
(V
DD
= AV
DD
= 5 V
6
5%, GND = AGND = 0 V, T
AMB
= –40
8
C to +85
8
C,
RECOMMENDED OPERATING CONDITIONS
CLKIN = 13 MHz, unless otherwise noted)
B Grade
Parameter
Min
Max
Unit
V
DD
Digital Supply Voltage
4.75
5.25
V
AV
DD
Analog Supply Voltage
4.75
5.25
V
T
AMB
Ambient Operating Temperature
–40
+85
°
C
ELECTRICAL CHARACTERISTICS
Parameter
Test Conditions
Min
Max
Unit
V
IH
HI-Level Input Voltage
1, 2, 3
@ V
DD
= max
2.0
V
V
IL
LO-Level Input Voltage
1, 2, 3
@ V
DD
= min
0.8
V
V
OH
HI-Level Output Voltage
1, 3, 4, 5, 6
@ V
DD
= min, I
OH
= –1.0 mA
2.4
V
@ V
DD
= min, I
OH
= –0.1 mA
V
DD
– 0.3
V
V
OL
LO-Level Output Voltage
1, 3, 4, 5, 6
@ V
DD
= min, I
OL
= 2.0 mA
0.4
V
V
OH
HI-Level Output Voltage
5
@ V
DD
= min, I
OH
= –10.0 mA
2.4
V
V
OL
LO-Level Output Voltage
5
@ V
DD
= min, I
OL
= 10.0 mA
1.2
V
I
IH
HI-Level Input Current
7
@ V
DD
= max, V
IN
= V
DD
max
10
m
A
I
IH
HI-Level Input Current
8
@ V
DD
= max, V
IN
= V
DD
max
100
m
A
I
IH
HI-Level Input Current
9
@ V
DD
= max, V
IN
= V
DD
max
10
m
A
I
IL
LO-Level Input Current
7
@ V
DD
= max, V
IN
= 0 V
10
m
A
I
IL
LO-Level Input Current
8
@ V
DD
= max, V
IN
= 0 V
10
m
A
I
IL
LO-Level Input Current
9
@ V
DD
= max, V
IN
= 0 V
100
m
A
I
OZH
HI-Level Three-State Leakage Current
10
@ V
DD
= max, V
IN
= V
DD
max
10
m
A
I
OZL
LO-Level Three-State Leakage Current
10
@ V
DD
= max, V
IN
= 0 V
10
m
A
I
DD
Digital Supply Current (Idle)
11
@ V
DD
= max
40
mA
I
DD
Digital Supply Current (Dynamic)
12
@ V
DD
= max
110
mA
I
DD
Analog Supply Current
@ AV
DD
= max
60
mA
C
I
Input Pin Capacitance
13
V
IN
= 2.5 V, f
IN
= 1 MHz,
8
pF
T
AMB
= +25
°
C
C
O
Output Pin Capacitance
13, 14
V
IN
= 2.5 V, f
IN
= 1 MHz,
8
pF
T
AMB
= +25
°
C
NOTES
1
Bidirectional pins: D0–D23, RFS0, RFS1, TFS0, TFS1, SCLK0 and SCLK1, PIO0–PIO11.
2
Input only pins:
PWMTRIP
, PWMPOL,
PWMSR
,
RESET
, EIA, EIB, EIZ, EIS, ETU0, ETU1, DR1A, DR1B, DR0, CLKIN, CONVST, MMAP, BMODE,
BR
and
PWD
.
3
Programmable I/O Pins (PIO0–PIO11).
4
Output pins: PWMSYNC, AUX0, AUX1, CLKOUT, DT0, DT1,
BG
,
BGH
,
PMS
,
DMS
,
BMS
,
RD
,
WR
, PWDACK and A0–A13.
5
Output pins: AH, AL, BH, BL, CH and CL.
6
Although specified for TTL outputs, all ADMC401 outputs are CMOS-compatible and will drive to V
DD
–0.3 V and GND+0.3 V assuming no dc loads.
7
Input only pins
RESET
, EIA, EIB, EIZ, EIS, ETU0, ETU1, DR1A, DR1B, DR0, CLKIN, CONVST, MMAP, BMODE,
BR
and
PWD
.
8
Input pins with internal pull-down PIO0–PIO11 and
PWMTRIP
.
9
Input pins with internal pull-up, PWMPOL and
PWMSR
.
10
Three-statable pins: A0–A13, D0–D23,
PMS
,
DMS
,
BMS
,
RD
,
WR
, DT0, DT1, RFS0, RFS1, TFS0, TFS1, SCLK0, SCLK1.
11
Idle refers execution of the IDLE instruction. Deasserted pins are driven to V
DD
or GND. Current reflects device operation with CLKOUT disabled.
12
Current reflects device operating with no output loads.
13
Guaranteed but not tested.
14
Output Pin Capacitance is the capacitive load for any three-state output pin.
Specifications subject to change without notice.
–2–
REV. A
ADMC401
ANALOG-TO-DIGITAL CONVERTER
Parameter
(V
DD
= AV
DD
= 5 V
6
5%, GND = AGND = 0 V, T
AMB
= –40
8
C to +85
8
C, CLKIN = 13 MHz,
VIN0 to VIN7 = 4.0 V p-p, V
REF
= 2.0 V, unless otherwise noted)
Test Conditions
Min
Typ
Max
Unit
AC SPECIFICATIONS
SNR
Signal to Noise Ratio
f
IN
= 1.0 kHz
68
70
dB
SNRD
Signal to Noise and Distortion
f
IN
= 1.0 kHz
66
69
dB
THD
Total Harmonic Distortion
f
IN
= 1.0 kHz
–76
–70
dB
CTLK
Channel-Channel Crosstalk
f
IN
= 1.0 kHz
–89
–72
dB
CMRR
Common-Mode Rejection Ratio
–90
–72
dB
PSRR
Power Supply Rejection Ratio
0.025
0.1
% FSR
ACCURACY
INL
Integral Nonlinearity
± 0.6
± 1.5
LSB
DNL
Differential Nonlinearity
± 0.5
± 1.0
LSB
No Missing Codes
12
Bits Guaranteed
Zero Error
0.1
0.25
% FSR
Gain Error
1
0.4
1.0
% FSR
TEMPERATURE DRIFT
Zero Error
0.025
% FSR
Gain Error
1
0.025
% FSR
INPUT VOLTAGE
V
IN
Voltage Span
4.0
V p-p
C
IN
Input Capacitance
2
10
pF
CONVERSION TIME
t
CONV
Total Conversion Time
All 8 Channels
1.88
ms
NOTES
1
Excludes Internal Voltage Reference Error.
2
Analog Input Pins VIN0 to VIN7.
Typical values are neither tested nor guaranteed.
Specifications subject to change without notice.
VOLTAGE REFERENCE
Parameter
(V
DD
= AV
DD
= 5 V
6
5%, GND = AGND = 0 V, T
AMB
= –40
8
C to +85
8
C, CLKIN = 13 MHz, VIN0 to VIN7 =
4.0 V p-p, V
REF
= 2.0 V, unless otherwise noted)
Test Conditions
Min
Typ
Max
Unit
V
REF
Output Voltage Reference
SENSE = REFCOM
1.96
2.0
2.04
V
Output Voltage Tolerance
1
SENSE = REFCOM
6
mV
Output Current
1.0
mA
Load Regulation
1.0 mA Load Current
0.3
1.5
mV
Power Supply Rejection Ratio
0.1
1.5
mV
Reference Input Resistance
8
kW
NOTES
1
Relative tolerance due to temperature change, T
MIN
to T
MAX
.
Specifications subject to change without notice.
POWER-ON RESET
Parameter
(GND = AGND = 0 V, T
AMB
= –40
8
C to +85
8
C, CLKIN = 13 MHz, unless otherwise noted)
Test Conditions
Min
Typ
Max
Unit
V
RST
Reset Threshold Voltage
3.25
4.0
V
V
HYST
Hysteresis Voltage
75
mV
Specifications subject to change without notice.
REV. A
–3–
ADMC401
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Output Voltage Swing . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Operating Temperature Range (Ambient) . . . . –40
°
C to +85
°
C
Storage Temperature Range . . . . . . . . . . . . . –65
°
C to +150
°
C
C
*Stresses above those listed under absolute maximum ratings may cause permanent
damage to the device. These are stresses only; functional operation of the device
at these or any other conditions above those indicated in the operational section of
this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
°
ORDERING GUIDE
Temperature
Instruction
Package
Package
Model
Range
Rate
Description
Option
ADMC401BST
–40
C to +85
°
C
26 MHz
144-Lead Plastic Thin Quad Flatpack (LQFP)
ST-144
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADMC401 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
Timing Parameters
GENERAL NOTES
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results for
an individual device, the values given in this data sheet reflect
statistical variations and worst cases. Consequently, you cannot
meaningfully add up parameters to derive longer times.
MEMORY REQUIREMENTS
This chart links common memory device specification names
and ADMC401 timing parameters for your convenience.
Common
Parameter
Memory Device
Name
Function
Specification Name
TIMING NOTES
Switching characteristics specify how the processor changes its
signals. You have no control over this timing; it is dependent on
the internal design. Timing requirements apply to signals that
are controlled outside the processor, such as the data input for a
read operation.
Timing requirements guarantee that the processor operates
correctly with another device. Switching characteristics tell you
what the device will do under a given circumstance. Also, use
the switching characteristics to ensure any timing requirement
of a device connected to the processor (such as memory) is
satisfied.
t
ASW
A0–A13,
DMS
,
PMS
Address Setup to
Setup before
WR
Low
Write Start
t
AW
A0–A13,
DMS
,
PMS
Address Setup to
before
WR
Deasserted
Write End
t
WRA
A0–A13,
DMS
,
PMS
Address Hold Time
Hold after
WR
Deasserted
t
DW
Data Setup before
WR
High Data Setup Time
t
DH
Data Hold after
WR
High Data Hold Time
t
RDD
RD
Low to Data Valid
OE
to Data Valid
t
AA
A0–A13,
DMS
,
PMS
,
Address Access Time
BMS
to Data Valid
–4–
REV. A
Lead Temperature (5 sec) . . . . . . . . . . . . . . . . . . . . . . +280
°
ADMC401
Parameter
Min
Max
Unit
Clock Signals
t
CK
is defined as 0.5t
CKI.
The ADMC401 uses an input clock
with a frequency equal to half the instruction rate; a 13 MHz
clock (which is equivalent to 76.9 ns) yields a 38.5 ns processor
cycle (equivalent to 26 MHz). t
CK
values within the range of
0.5t
CKI
period should be substituted for all relevant timing
parameters to obtain specification value.
Example: t
CKH
= 0.5t
CK
– 10 ns = 0.5 (38.5 ns) – 10 ns = 9.25 ns.
Timing Requirements:
t
CKI
CLKIN Period
76.9
150
ns
t
CKIL
CLKIN Width Low
20
ns
t
CKIH
CLKIN Width High
20
ns
Switching Characteristics:
t
CKL
CLKOUT Width Low
0.5t
CK
– 10
ns
t
CKH
CLKOUT Width High
0.5t
CK
– 10
ns
t
CKOH
CLKIN High to CLKOUT High
0
20
ns
Control Signals
Timing Requirement:
t
RSP
RESET
Width Low
5t
CK
1
ns
PWM Shutdown Signals
Timing Requirements:
t
PWMTPW
PWMTRIP
Width Low
t
CK
ns
t
PIOPWM
PIO Width Low
2t
CK
ns
ADC Signals
T
iming Requirements:
t
CSI
Internal Convert Start Width High
2t
CK
ns
t
CSE
External Convert Start Width High
2t
CK
ns
NOTE
1
Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal
oscillator start-up time).
t
CKI
t
CKIH
CLKIN
t
CKIL
t
CKOH
t
CKH
CLKOUT
t
CKL
Figure 1. Clock Signals
REV. A
–5–
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