ADMCF326 0

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a
28-Lead Flash Memory
DSP Motor Controller
ADMCF326
TARGET APPLICATIONS
Washing Machines, Refrigerator Compressors, Fans,
Pumps, Industrial Variable Speed Drives
Three-Phase 16-Bit PWM Generator
16-Bit Center-Based PWM Generator
Programmable Dead Time and Narrow Pulse Deletion
Edge Resolution to 50 ns
150 Hz Minimum Switching Frequency
Double/Single Duty Cycle Update Mode Control
Programmable PWM Pulsewidth
Special Crossover Function for Brushless DC Motors
Individual Enable and Disable for Each PWM Output
High Frequency Chopping Mode for Transformer
Coupled Gate Drives
External PWMTRIP Pin
Integrated ADC Subsystem
Six Analog Inputs
Acquisition Synchronized to PWM Switching Frequency
Internal Voltage Reference
9-Pin Digital I/O Port
Bit Configurable as Input or Output
Change of State Interrupt Support
Two 8-Bit Auxiliary PWM Timers
Synthesized Analog Output
Programmable Frequency
0% to 100% Duty Cycle
Two Programmable Operational Modes
Independent Mode/Offset Mode
16-Bit Watchdog Timer
Programmable 16-Bit Internal Timer with Prescaler
Double Buffered Synchronous Serial Port
Hardware Support for UART Emulation
Integrated Power-On Reset Function Options
28-Lead SOIC Package
MOTOR TYPES
AC Induction Motors
Permanent Magnet Synchronous Motors (PMSM)
Brushless DC Motors (BDCM)
FEATURES
20 MIPS Fixed-Point DSP Core
Single Cycle Instruction Execution (50 ns)
ADSP-21xx Family Code Compatible
Independent Computational Units
ALU
Multiplier/Accumulator
Barrel Shifter
Multifunction Instructions
Single Cycle Context Switch
Powerful Program Sequencer
Zero Overhead Looping
Conditional Instruction Execution
Two Independent Data Address Generators
Memory Configuration
512
24-Bit Program Memory RAM
512
16-Bit Data Memory RAM
4K
24-Bit Program Memory ROM
24-Bit Program Flash Memory
Three Independent Programmable Sectors
Security Lock Bit
10K Erase/Program Cycles
FUNCTIONAL BLOCK DIAGRAM
ADSP-2100 BASE
ARCHITECTURE
MEMORY BLOCK
PROGRAM
ROM
4K
PROGRAM
FLASH
4K
DATA
ADDRESS
GENERATORS
DAG 1 DAG 2
24
24
6
ANALOG
INPUTS
16-BIT
THREE-
PHASE
PWM
PROGRAM
SEQUENCER
PROGRAM
RAM
512
24
DATA
MEMORY
512
16
VREF
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
ARITHMETIC UNITS
SHIFTER
SERIAL PORT
SPORT 1
9-BIT
PIO
2
8-BIT
AUX
PWM
WATCH-
DOG
TIMER
POR
TIMER
ALU
MAC
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
4K
2.5V
 ADMCF326–SPECIFICATIONS
(V
DD
= 5 V
5%, GND = 0 V, T
A
= –40
C to +85
C, CLKIN = 10 MHz, unless
otherwise noted)
ANALOG-TO-DIGITAL CONVERTER
Parameter
Min
Typ
Max
Unit
Conditions/Comments
Signal Input
0.3
3.5
V
V1, V2, V3, VAUX0, VAUX1, VAUX2
Resolution
1
12
Bits
Linearity Error
2
2
4
Bits
Zero Offset
2
–20
0
+20
mV
Channel-to-Channel Comparator Match
2
20
mV
Comparator Delay
600
ns
ADC High Level Input Current
2
10
µA
V
IN
= 3.5 V
ADC Low Level Input Current
2
–10
µ
A
V
IN
= 0.0 V
NOTES
1
Resolution varies with PWM switching frequency (double update mode) 78.1 kHz = 8 bits, 4.9 kHz = 12 bits.
2
2.44 kHz sample frequency, V1, V2, V3, VAUX0, VAUX1, VAUX2.
Specifications subject to change without notice.
ELECTRICAL CHARACTERISTICS
Parameter
Min
Typ
Max
Unit
Conditions/Comments
V
IL
Low Level Input Voltage
0.8
V
V
IH
High Level Input Voltage
2
V
V
OL
Low Level Output Voltage
1
0.4
V
I
OL
= 2 mA
V
OL
Low Level Output Voltage
2
0.8
V
I
OL
= 2 mA
V
OH
High Level Output Voltage
4
V
I
OH
= –0.5 mA
I
IL
Low Level Input Current
3
–120
µ
A
V
IN
= 0 V
I
IL
Low Level Input Current
–10
µ
A
V
IN
= 0 V
I
IH
High Level Input Current
4
90
µA
V
IN
= V
DD
I
IH
High Level Input Current
10
µ
A
V
IN
= V
DD
I
OZH
High Level Three-State Leakage Current
5
90
µ
A
V
IN
= V
DD
I
OZL
Low Level Three-State Leakage Current
5
–10
µ
A
V
IN
= 0
I
IL
Low Level
PWMTRIP
Current
–10
µ
A
@ V
DD
= Max, V
IN
= 0 V
I
DD
Supply Current (Idle)
6
41
mA
I
DD
Supply Current (Dynamic)
6
108
mA
Supply Current Programming
6
123
mA
NOTES
1
Output Pins PIO0–PIO8, AH, AL, BH, BL, CH, CL.
2
XTAL Pin.
3
Internal Pull-Up,
RESET
.
4
Internal Pull-Down,
PWMTRIP
, PIO0–PIO8.
5
Three stateable pins DT1, RFS1, TFS1, SCLK1.
6
Outputs not Switching.
Specifications subject to change without notice.
CURRENT SOURCE
1
Parameter
Min
Typ
Max
Unit
Conditions/Comments
Programming Resolution
3
Bits
Default Current
2
65
83
95
µ
A
ICONST_TRIM = 0x00
Tuned Current
95
100
105
µ
A
NOTES
1
For ADC Calibration.
2
0.3 V to 3.5 V ICONST Voltage.
Specifications subject to change without notice.
–2–
REV. 0
ADMCF326
VOLTAGE REFERENCE
Parameter
Min
Typ
Max
Unit
Conditions/Comments
Voltage Level (V
REF
)
2.40
2.50
2.60
V
2.45
2.50
2.55
V
T
A
= 25°C to 85°C SOIC
Output Voltage Drift
35
ppm/°C
Specifications subject to change without notice.
POWER-ON RESET
Parameter
Min
Typ
Max
Unit
Conditions/Comments
Reset Threshold (V
RST
)
3.2
3.7
4.2
V
Hysteresis (V
HYST
)
100
mV
Reset Active Timeout Period (
t
RST
)
3.2
1
ms
NOTES
1
2
16
CLKOUT Cycles.
Specifications subject to change without notice.
FLASH MEMORY
Parameter
Min
Typ
Max
Unit
Conditions/Comments
Endurance
10,000
Cycles
Cycle = Erase/Program/Verify
Data Retention
15
Years
Program and Erase Operating Temperature
0
85
C
Read Operating Temperature
–40
+85
C
Specifications subject to change without notice.
REV. 0
–3–
ADMCF326
TIMING PARAMETERS
Parameter
Min
Max
Unit
Clock Signals
Signal t
CK
is defined as 0.5 t
CKIN
. The ADMCF326 uses an input clock with a
frequency equal to half the instruction rate; a 10 MHz input clock (which is
equivalent to 100 ns) yields a 50 ns processor cycle (equivalent to 20 MHz). When
t
CK
values are within the range of 0.5 t
CKIN
period, they should be substituted for
all relevant timing parameters to obtain specification value.
Example: t
CKH
= 0.5 t
CK
– 10 ns = 0.5 (50 ns) – 10 ns = 15 ns.
Timing Requirements:
t
CKIN
CLKIN Period
100
150
ns
t
CKIL
CLKIN Width Low
20
ns
t
CKIH
CLKIN Width High
20
ns
Switching Characteristics:
t
CKL
CLKOUT Width Low
0.5 t
CK
– 10
ns
t
CKH
CLKOUT Width High
0.5 t
CK
– 10
ns
t
CKOH
CLKIN High to CLKOUT High
0
20
ns
Control Signals
Timing Requirement:
t
RSP
RESET
Width Low
5 t
CK
1
ns
PWM Shutdown Signals
Timing Requirement:
t
PWMTPW
PWMTRIP
Width Low
t
CK
ns
NOTES
1
Applies after power-up sequence is complete.
t
CKIN
t
CKIH
CLKIN
t
CKIL
t
CKOH
t
CKH
CLKOUT
t
CKL
Figure 1. Clock Signals
–4–
REV. 0
ADMCF326
Parameter
Min
Max
Unit
Serial Ports
Timing Requirements:
t
SCK
SCLK Period
100
ns
t
SCS
DR/TFS/RFS Setup before SCLK Low
15
ns
t
SCH
DR/TFS/RFS Hold after SCLK Low
20
ns
t
SCP
SCLK
IN
Width
40
ns
Switching Characteristics
:
t
CC
CLKOUT High to SCLK
OUT
0.25 t
CK
0.25 t
CK
+ 20
ns
t
SCDE
SCLK High to DT Enable
0
ns
t
SCDV
SCLK High to DT Valid
30
ns
t
RH
TFS/RFS
OUT
Hold after SCLK High
0
ns
t
RD
TFS/RFS
OUT
Delay from SCLK High
30
ns
t
SCDH
DT Hold after SCLK High
0
ns
t
SCDD
SCLK High to DT Disable
30
ns
t
TDE
TFS (Alt) to DT Enable
0
ns
t
TDV
TFS (Alt) to DT Valid
25
ns
t
RDV
RFS (Multichannel, Frame Delay Zero) to DT Valid
30
ns
Specifications subject to change without notice.
CLKOUT
t
CC
t
CC
t
SCK
SCLK
t
SCS
t
SCH
t
SCP
t
SCP
DR
RFS
IN
TFS
IN
t
RD
t
RH
RFS
OUT
TFS
OUT
t
SCDV
t
SCDD
t
SCDE
t
SCDH
DT
t
TDE
t
TDV
TFS
(ALTERNATE
FRAME MODE)
t
RDV
RFS
(MULTICHANNEL MODE,
FRAME DELAY 0 [MFD = 0])
Figure 2. Serial Port Timing
REV. 0
–5–
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