AD7475 95 a

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a
1 MSPS,
12-Bit ADCs
AD7475/AD7495
FEATURES
Fast Throughput Rate: 1 MSPS
Specified for V
DD
of 2.7 V to 5.25 V
Low Power:
4.5 mW Max at 1 MSPS with 3 V Supplies
10.5 mW Max at 1 MSPS with 5 V Supplies
Wide Input Bandwidth:
68 dB SNR at 300 kHz Input Frequency
Flexible Power/Serial Clock Speed Management
No Pipeline Delays
High-Speed Serial Interface SPIâ„¢/QSPIâ„¢/
MICROWIREâ„¢/DSP-Compatible
On-Board Reference 2.5 V (AD7495 Only)
Standby Mode: 1
FUNCTIONAL BLOCK DIAGRAMS
V
DD
V
IN
T/H
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
REF IN
SCLK
CONTROL
LOGIC
SDATA
CS
A Max
AD7475
V
DRIVE
8-Lead
SOIC and SOIC Packages
GND
APPLICATIONS
Battery-Powered Systems
Personal Digital Assistants
Medical Instruments
Mobile Communications
Instrumentation and Control Systems
Data Acquisition Systems
High-Speed Modems
Optical Sensors
V
DD
V
IN
T/H
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
REF OUT
BUF
SCLK
CONTROL
LOGIC
SDATA
2.5V
REFERENCE
CS
GENERAL DESCRIPTION
The AD7475/AD7495 are 12-bit high-speed, low-power,
successive-approximation ADCs. The parts operate from a single
2.7 V to 5.25 V power supply and feature throughput rates up to
1 MSPS. The parts contain a low-noise, wide bandwidth track/hold
amplifier that can handle input frequencies in excess of 1 MHz.
The conversion process and data acquisition are controlled using
CS
and the serial clock allowing the devices to interface with
microprocessors or DSPs. The input signal is sampled on the
falling edge of
CS
and conversion is also initiated at this point.
There are no pipelined delays associated with the part.
The AD7475/AD7495 use advanced design techniques to achieve
very low power dissipation at high throughput rates. With 3 V
supplies and 1 MSPS throughput rate, the AD7475 consumes just
1.5 mA, while the AD7495 consumes 2 mA. With 5 V supplies
and 1 MSPS, the current consumption is 2.1 mA for the AD7475
and 2.6 mA for the AD7495.
The analog input range for the part is 0 V to REF IN. The 2.5 V
reference for the AD7475 is applied externally to the REF IN pin
while the AD7495 has an on-board 2.5 V reference. The conver-
sion time is determined by the SCLK frequency.
AD7495
V
DRIVE
GND
PRODUCT HIGHLIGHTS
1. High throughput with low power consumption. The
AD7475 offers 1 MSPS throughput rates with 4.5 mW
power consumption.
2. Single-supply operation with V
DRIVE
function. The AD7475/
AD7495 operate from a single 2.7 V to 5.25 V supply. The
V
DRIVE
function allows the serial interface to connect directly
to either 3 V or 5 V processor systems independent of V
DD
.
3. Flexible power/serial clock speed management. The con-
version rate is determined by the serial clock, allowing the
conversion time to be reduced through the serial clock speed
increase. The part also features shutdown modes to maximize
power efficiency at lower throughput rates. This allows the
average power consumption to be reduced while not convert-
ing. Power consumption is 1 µA when in full shutdown.
4. No pipeline delay. The part features a standard successive-
approximation ADC with accurate control of the sampling
instant via a
CS
input and once off conversion control.
MICROWIRE is a trademark of National Semiconductor Corporation.
SPI and QSPI are trademarks of Motorola, Inc.
REV.A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
AD7475/AD7495–SPECIFICATIONS
1
AD7475–SPECIFICATIONS
1
Parameter
(V
DD
= 2.7 V to 5.25 V, V
DRIVE
= 2.7 V to 5.25 V, REF IN = 2.5 V, f
SCLK
= 20 MHz unless otherwise
noted; T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
A Version
1
B Version
1
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
Signal to Noise + Distortion Ratio
68
68
dB min
f
IN
= 300 kHz Sine Wave, f
SAMPLE
= 1 MSPS
(SINAD)
Total Harmonic Distortion (THD) –75
–75
dB max
f
IN
= 300 kHz Sine Wave, f
SAMPLE
= 1 MSPS
Peak Harmonic or Spurious Noise
–76
–76
dB max
f
IN
= 300 kHz Sine Wave, f
SAMPLE
= 1 MSPS
(SFDR)
Intermodulation Distortion (IMD)
Second Order Terms
–78
–78
dB typ
Third Order Terms
–78
–78
dB typ
Aperture Delay
10
10
ns typ
Aperture Jitter
50
50
ps typ
Full Power Bandwidth
8.3
8.3
MHz typ
@ 3 dB
Full Power Bandwidth
1.3
1.3
MHz typ
@ 0.1 dB
DC ACCURACY
Resolution
12
12
Bits
Integral Nonlinearity
± 1.5
± 1
LSB max
@ 5 V (typ @ 3 V)
± 0.5
± 0.5
LSB typ
@ 25°C
Differential Nonlinearity
+1.5/–0.9
+1.5/–0.9
LSB max
@ 5 V Guaranteed No Missed Codes to 12 Bits
(typ @ 3 V)
± 0.5
± 0.5
LSB typ
@ 25°C
Offset Error
± 8
± 8
LSB max
Typically ± 2.5 LSB
Gain Error
± 3
± 3
LSB max
ANALOG INPUT
Input Voltage Ranges
0 to REF IN
Volts
DC Leakage Current
±
1
±
1
µ
A max
Input Capacitance
20
20
pF typ
REFERENCE INPUT
REF IN Input Voltage Range
2.5
2.5
Volts
±
1% for Specified Performance
DC Leakage Current
± 1
± 1
µA max
Input Capacitance
20
20
pF typ
LOGIC INPUTS
Input High Voltage, V
INH
V
DRIVE
– 1
V
DRIVE
– 1
V min
Input Low Voltage, V
INL
0.4
0.4
V max
Input Current, I
IN
±
1
±
1
µ
A max
Typically 10 nA, V
IN
= 0 V or V
DRIVE
Input Capacitance, C
IN
2
10
10
pF max
LOGIC OUTPUTS
Output High Voltage, V
OH
V
DRIVE
– 0.2
V min
I
SOURCE
= 200
A; V
DRIVE
= 2.7 V to 5.25 V
Output Low Voltage, V
OL
0.4
0.4
V max
I
SINK
= 200 µA
Floating-State Leakage Current
± 10
± 10
µA max
Floating-State Output Capacitance
2
10
10
pF max
Output Coding
Straight (Natural) Binary
CONVERSION RATE
Conversion Time
800
800
ns max
16 SCLK Cycles with SCLK at 20 MHz
Track/Hold Acquisition Time
300
300
ns max
Sine Wave Input
325
325
ns max
Full-Scale Step Input
Throughput Rate
1
1
MSPS max See Serial Interface Section
POWER REQUIREMENTS
V
DD
2.7/5.25
2.7/5.25
V min/max
V
DRIVE
2.7/5.25
2.7/5.25
V min/max
I
DD
3
Digital I/Ps = 0 V or V
DRIVE
Normal Mode (Static)
750
750
A typ
V
DD
= 2.7 V to 5.25 V. SCLK On or Off
Normal Mode (Operational)
2.1
2.1
mA max
V
DD
= 4.75 V to 5.25 V. f
SAMPLE
= 1 MSPS
1.5
1.5
mA max
V
DD
= 2.7 V to 3.6 V. f
SAMPLE
= 1 MSPS
Partial Power-Down Mode
450
450
µA typ
f
SAMPLE
= 100 kSPS
Partial Power-Down Mode
100
100
µ
A max
(Static)
Full Power-Down Mode
1
1
µ
A max
SCLK On or Off
–2–
REV. A
µ
AD7475–SPECIFICATIONS (continued)
Parameter
AD7475/AD7495
A Version
1
B Version
1
Unit
Test Conditions/Comments
POWER REQUIREMENTS
(continued)
Power Dissipation
3
Normal Mode (Operational)
10.5
10.5
mW max
V
DD
= 5 V. f
SAMPLE
= 1 MSPS
4.5
4.5
mW max
V
DD
= 3 V. f
SAMPLE
= 1 MSPS
Partial Power-Down (Static)
500
500
W max
V
DD
= 5 V
300
300
W max
V
DD
= 3 V
Full Power-Down
5
5
W max
V
DD
= 5 V
3
3
W max
V
DD
= 3 V
NOTES
1
Temperature ranges as follows: A, B Versions: –40
C to +85
C.
2
Sample tested @ 25
C to ensure compliance.
3
See Power Versus Throughput Rate section.
Specifications subject to change without notice.
AD7495–SPECIFICATIONS
1
Parameter
(V
DD
= 2.7 V to 5.25 V, V
DRIVE
= 2.7 V to 5.25 V, f
SCLK
= 20 MHz unless otherwise noted; T
A
= T
MIN
to
T
MAX
, unless otherwise noted.)
A Version
1
B Version
1
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
Signal to Noise + Distortion
68
68
dB min
f
IN
= 300 kHz Sine Wave, f
SAMPLE
= 1 MSPS
(SINAD)
Total Harmonic Distortion (THD) –75
–75
dB max
f
IN
= 300 kHz Sine Wave, f
SAMPLE
= 1 MSPS
Peak Harmonic or Spurious Noise –76
–76
dB max
f
IN
= 300 kHz Sine Wave, f
SAMPLE
= 1 MSPS
(SFDR)
Intermodulation Distortion (IMD)
Second Order Terms
–78
–78
dB typ
Third Order Terms
–78
–78
dB typ
Aperture Delay
10
10
ns typ
Aperture Jitter
50
50
ps typ
Full Power Bandwidth
8.3
8.3
MHz typ
@ 3 dB
Full Power Bandwidth
1.3
1.3
MHz typ
@ 0.1 dB
DC ACCURACY
Resolution
12
12
Bits
Integral Nonlinearity
±
1.5
±
1
LSB max
@ 5 V (typ @ 3 V)
±0.5
±0.5
LSB typ
@ 25°C
Differential Nonlinearity
+1.5/–0.9
+1.5/–0.9
LSB max
@ 5 V Guaranteed No Missed Codes to 12 Bits
(typ @ 3 V)
±0.6
±0.6
LSB typ
@ 25°C
Offset Error
±
8
±
8
LSB max
Typically
±
2.5 LSB
Gain Error
± 7
± 7
LSB max
Typically ± 2.5 LSB
ANALOG INPUT
Input Voltage Ranges
0 to 2.5
0 to 2.5
Volts
DC Leakage Current
±
1
±
1
µ
A max
Input Capacitance
20
20
pF typ
REFERENCE OUTPUT
REF OUT Output Voltage
2.4625/2.5375 2.4625/2.5375 V min/max
REF OUT Impedance
10
10
Ω typ
REF OUT Temperature Coefficient 50
50
ppm/
C typ
LOGIC INPUTS
Input High Voltage, V
INH
V
DRIVE
– 1
V
DRIVE
– 1
V min
Input Low Voltage, V
INL
0.4
0.4
V max
Input Current, I
IN
±
1
±
1
µ
A max
Typically 10 nA, V
IN
= 0 V or V
DRIVE
Input Capacitance, C
IN
2
10
10
pF max
LOGIC OUTPUTS
Output High Voltage, V
OH
V
DRIVE
– 0.2
V min
I
SOURCE
= 200 µA; V
DD
= 2.7 V to 5.25 V
Output Low Voltage, V
OL
0.4
0.4
V max
I
SINK
= 200
µ
A
Floating-State Leakage Current
±10
±10
µA max
Floating-State Output Capacitance
2
10
10
pF max
Output Coding
Straight (Natural) Binary
REV. A
–3–
AD7475/AD7495–SPECIFICATIONS
1
AD7495–SPECIFICATIONS (continued)
Parameter
A Version
1
B Version
1
Unit
Test Conditions/Comments
CONVERSION RATE
Conversion Time
800
800
ns max
16 SCLK Cycles with SCLK at 20 MHz
Track/Hold Acquisition Time
300
300
ns max
Sine Wave Input
325
325
ns max
Full-Scale Step Input
Throughput Rate
1
1
MSPS max See Serial Interface Section
POWER REQUIREMENTS
V
DD
2.7/5.25
2.7/5.25
V min/max
V
DRIVE
2.7/5.25
2.7/5.25
V min/max
I
DD
Digital I/Ps = 0 V or V
DRIVE
Normal Mode (Static)
1
1
mA typ
V
DD
= 2.7 V to 5.25 V. SCLK On or Off
Normal Mode (Operational)
2.6
2.6
mA max
V
DD
= 4.75 V to 5.25 V. f
SAMPLE
= 1 MSPS
2
2
mA max
V
DD
= 2.7 V to 3.6 V. f
SAMPLE
= 1 MSPS
Partial Power-Down Mode
650
650
µA typ
f
SAMPLE
= 100 kSPS
Partial Power-Down Mode
230
230
µA max
(Static)
Full Power-Down Mode
1
1
µA max
(Static) SCLK On or Off
Power Dissipation
3
Normal Mode (Operational)
13
13
mW max
V
DD
= 5 V. f
SAMPLE
= 1 MSPS
6
6
mW max
V
DD
= 3 V. f
SAMPLE
= 1 MSPS
Partial Power-Down (Static)
1.15
1.15
mW max
V
DD
= 5 V
690
690
µW max
V
DD
= 3 V
Full Power-Down
5
5
µW max
V
DD
= 5 V
3
3
µW max
V
DD
= 3 V
NOTES
1
Temperature ranges as follows: A, B Versions: –40
C to +85
C.
2
Sample tested @ 25
C to ensure compliance.
3
See Power Versus Throughput Rate section.
Specifications subject to change without notice.
TIMING SPECIFICATIONS
1
(V
DD
= 2.7 V to 5.25 V, V
DRIVE
= 2.7 V to 5.25 V, REF IN = 2.5 V (AD7475); T
A
= T
MIN
to T
MAX
, unless
otherwise noted.)
Limit at T
MIN
, T
MAX
Parameter
AD7475/AD7495
Unit
Description
f
SCLK
2
10
kHz min
20
MHz max
t
CONVERT
16 × t
SCLK
t
SCLK
= 1/f
SCLK
800
ns max
f
SCLK
= 20 MHz
t
QUIET
100
ns min
Minimum Quiet Time Required between Conversions
t
2
10
ns min
CS
to SCLK Setup Time
t
3
3
22
ns max
Delay from
CS
Until SDATA 3-State Disabled
t
4
3
40
ns max
Data Access Time after SCLK Falling Edge
t
5
0.4 t
SCLK
ns min
SCLK Low Pulsewidth
t
6
0.4 t
SCLK
ns min
SCLK High Pulsewidth
t
7
10
ns min
SCLK to Data Valid Hold Time
t
8
4
10
ns min
SCLK Falling Edge to SDATA High Impedance
45
ns max
SCLK Falling Edge to SDATA High Impedance
t
9
4
20
ns max
CS
Rising Edge to SDATA High Impedance
t
POWER-UP
20
µs max
Power-Up Time from Full Power-Down AD7475
650
µs max
Power-Up Time from Full Power-Down AD7495
C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DRIVE
) and timed from a voltage level of 1.6 V.
2
Mark/Space ratio for the SCLK input is 40/60 to 60/40.
3
Measured with the load circuit of Figure 3 and defined as the time required for the output to cross 0.8 V or 2.0 V.
4
t
8
and t
9
are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 3. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times, t
8
and t
9
, quoted in the timing characteristics are
the true bus relinquish time of the part and are independent of the bus loading.
Specifications subject to change without notice.
–4–
REV. A
NOTES
1
Sample tested at 25
AD7475/AD7495
CS
t
CONVERT
t
2
t
6
B
SCLK
1
2
3
4
5
13
14
15
16
t
7
t
5
t
8
t
QUIET
t
3
t
4
SDATA
0
0
0
0
DB11
DB10
DB2
DB1
DB0
THREE-STATE
FOUR LEADING ZEROS
THREE-STATE
Figure 1. Serial Interface Timing Diagram
Timing Example 1
Having f
SCLK
= 20 MHz and a throughput of 1 MSPS gives a cycle
time of t
2
+ 12.5(1/f
SCLK
) + t
ACQ
= 1 µs. With t
2
= 10 ns min, this
leaves t
ACQ
to be 365 ns. This 365 ns satisfies the requirement of
300 ns for t
ACQ
. From Figure 2, t
ACQ
comprises of 2.5(1/f
SCLK
) + t
8
+ t
QUIET
, where t
8
= 45 ns. This allows a value of 195 ns for t
QUIET
,
satisfying the minimum requirement of 100 ns.
Timing Example 2
Having f
SCLK
= 5 MHz and a throughput of 315 KSPS, gives a
cycle time of t
2
+ 12.5(1/f
SCLK
) + t
ACQ
= 3.174
s.
With t
2
= 10 ns min, this leaves t
acq
to be 664 ns. This 664 ns
satisfies the requirement of 300 ns for t
ACQ
. From Figure 2, t
ACQ
is comprised of 2.5(1/f
SCLK
) + t
8
+ t
QUIET
, t
8
= 45 ns. This allows
a value of 119 ns for t
QUIET
satisfying the minimum requirement
of 100 ns. As in this example and with other slower clock values,
the signal may already be acquired before the conversion is
complete, but it is still necessary to leave 100 ns minimum
t
QUIET
between conversions. In Example 2 the signal should be
fully acquired at approximately Point C in Figure 2.
CS
t
CONVERT
t
2
t
6
B
C
SCLK
1
2
3
4
5
13
14
15
16
t
5
t
8
t
QUIET
45ns
t
ACQUISITION
12.5 (1/f
SCLK
)
10ns
1/THROUGHPUT
Figure 2. Serial Interface Timing Example
200
A
I
OL
TO OUTPUT
PIN
C
L
50pF
1.6V
200
A
I
OH
Figure 3. Load Circuit for Digital Output Timing Specifications
REV. A
–5–
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