AD8362 prn

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PRELIMINARY TECHNICAL DATA
a
60 dB TruPwr
LF – 2.7 GHz

Detector
Preliminary Technical Data
AD8362
FEATURES
True -Power (Root-Mea n-Squ are) Me as ure me nt
Temperature-Stable Linear-n-dB Resp ons e
Input Dynamic Range 6 0 dB
45 to 15 dBm CW Input re : 50
CHPF
INHI
INLO
x
2
CLPF
Flat Resp onse fro m LF to 2 .7 GHz, us eful to 3 GHz
High Acc uracy an d Line arity
Laser-rimme d S lope of 5 0 mV/dB
Modulation Independ e nt (GSM/W-CDMA/TDMA, etc.)
Operation from –40 o +5
Ω Ω
VTGT
x
2
VO UT
° °
C at V
S
of 4.5 t o 5.5 V
VSE T
Powers Dow n to 100
W
APPLICATIONS
Power Amplifier Line ariation/Control Loops
Multi-Carrier Trans mitter Power Co ntrol
Rx or Tx Signal Stre ngth Indication (RSSI , TSSI )
Ins trume ntation at LF, HF, VHF, UHF, L- and S -bands
AD8362
VREF
BIAS
VPOS
CO MM
PWDN
PRODUCT DESCR IPTION
The AD8362 is a true-RMS-responding power detector having a
60 dB measurement range, intended for use in a variety of high-
frequency communication and instrumentation systems where an
accurate response to signal power is required, regardless of signal
waveform. It is fully specified for use at frequencies up to 2.7
GHz. Signal inputs having RMS values from 1.26 mV to 1.26 V
(
When used in a power measurement mode, pin
VOUT
is simply tied to
VSET
, and the output is then proportional to the logarithm of the RMS
value of the input. Thus, the reading is scaled directly in decibels, and
is conveniently scaled 1 V per decade (50 mV per dB); other slopes
are easily arranged. The output can run from ground to a maximum of
about 0.1 V below the supply voltage, V
S
. High load currents can be
provided.
In controller modes, this low noise signal is used to vary the gain of
the host system’s RF amplifier, to restore a balance between the set-
point demand, determined by the voltage applied to the
VSET
pin, and
a sample of the actual RF power. The set-point voltage may optionally
be a baseband replica of the amplitude modulation, in which case the
effect is to remove the modulation component prior to detection and
low-pass filtering.
For general instrumentation applications, the corner frequency of the
averaging filter may be lowered without limit by the addition of an
external capacitor at pin
CLPF
. In this way, the AD8362 can be used to
determine the RMS value of a low-frequency signal having a complex
modulation envelope. The high-pass corner of the broadband amplifier
may also need to be lowered by a capacitor added at pin
CHPF
.
The input signal is first applied to a resistive ladder attenuator,
having twelve tap-points at about 5 dB intervals. These are
smoothly interpolated using a proprietary technique to implement
an accurate and continuously-variable attenuator, whose setting is
controlled by a voltage applied to pin
VSET
. The resulting signal
is applied to a high-performance broadband amplifier, the output
of which is measured by a wideband square-law detector cell
.
The resulting fluctuating output is then filtered and compared
with the output of an identical squarer, whose input is a fixed DC
voltage imported via pin
VTGT
, which will usually be tied to the
accurate reference of 1.25 V provided at pin
VREF
. In some
applications, the target voltage (and thus the log intercept) may
be altered. The resulting difference in the output of the two
squaring cells is then applied to a high-gain error amplifier (an
integrator) generating a voltage at pin
VOUT
which can run from
rail to rail.
A.
The chip powers up to its normal operating current of 18 mA at 25ºC
within less than 1
s.
The AD8362 is supplied in a 16-pin TSSOP package for operation over
the temperature range of -40
C to +85
C
.
Multiple patents pending
Rev. PrN 02/14/02
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its use;
nor for any infringements of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise under
any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 906, Norwood, MA 02062-106 U.S.A.
Tel: 781/3294700 www.analog.com
Fax: 781/326-8703 Analog Devices, Inc., 2002
µ µ
system) can be accepted. Large crest
factors, exceeding the requirements for accurate measurement of
CDMA signals, do not degrade accuracy. The AD8362 is easy to
use, requiring only a single supply of 5 V plus signal-coupling
capacitors (or, in some cases, a balun) and simple decoupling.
45 to +15 dBm in a 50
The AD8362 may be powered down by a logic voltage applied to the
PWDN
pin, when the current consumption is reduced to under 2
PRELIMINARY TECHNICAL DATA
AD8362-SPECIFICATIONS
(Unless otherwise noted, V
S
= 5 V, T=25°C, Z
o
= 50
Ω Ω
, differential input drive,
Parameters
Conditions
Min
Typ
Max Units
OVERALL FUNCTION
Maximum Input Frequency
2.7
GHz
Input Voltage Range
CW sine wave input
0.00126
1.26
Vrms
-58
+2
dBV
Equivalent input power re: 50
(see note 1)
-45
+15
dBm
Input Voltage Range
Single-ended drive, CW sine wave input
1.26
400 mVrms
-58
-8
dBV
Equivalent input power re: 50
(see note 1)
-45
+5
dBm
Measurement Linearity
2
Over central 50 dB range, 30 MHz
f
2.7 GHz
0.5
dB
Over central 60 dB range, 30 MHz
f
2.7 GHz
1
dB
RF INPUT INTERFACE
Pins
INHI
,
INLO
, ac coupled
Input Resistance
Single-ended drive, wrt
DECL
100
Differential drive
200
Input Impedance
(see performance curves)
TBD
OUTPUT INTERFACE
Pin
VOUT
Voltage Range
R
L
200
0.5
4.95
V
Source/Sink Current
VOUT
held at V
S
/2
TBD
mA
Small-signal Bandwidth
C
L
300 pF
TBD
MHz
Full-scale Slew Rate
C
L
300 pF
TBD
V/
s
Wideband Noise
CLPF
= xxx pF, f
SPOT
20 MHz
TBD
nV/
Hz
SET-POINT INPUT
Pin
VSET
Voltage Range
Corresponding to 1.126 mV – 1.26 Vrms input signal
0.5
3.5
V
Input Resistance
70
k
Logarithmic Scale Factor
f = 100 MHz, -40
C
T
A
85
C
50
mV/dB
Logarithmic Intercept
f = 100 MHz, -40
C
T
A
85
C, re: 1 Vrms
-66
dBV
re: 50
-53
dBm
Temperature Sensitivity
P
IN
= -10 dBm, slope and intercept errors combined
TBD
dB/
C
RMS TARGET SET
3
Pin
VTGT
Input Voltage Range
Measurement range = TBD dB
TBD
TBD
V
Input Bias Current
VTGT
= 1.25 V
-28
uA
VTGT
= 0 V
-52
uA
Incremental Input Resistance
52
k
Bandwidth of Target Channel To –3 dB point
260
MHz
VOLTAGE REFERENCE
Pin
VREF
Output Voltage
-40
C
T
A
85
C
1.25
V
Current Limit
Into a grounded load
TBD
mA
Power Supply Rejection Ratio
TBD
V/V
POWER DOWN INTERFACE Pin
PWDN
Logic Level to Enable
Logic LO enables
TBD
V
Logic Level to Disable
Logic HI disables
TBD
V
Input Current
Logic HI
TBD
uA
Logic LO
TBD
uA
Enable Time
From
PWDN
Low to
VOUT
within 10% of final value
TBD
TBD
us
Disable Time
From
PWDN
High to
VOUT
within 10% of final value
TBD
TBD
us
Rev. PrN 02/14/02
- 2 -
0 dBV = 1 Vrms)
PRELIMINARY TECHNICAL DATA
AD8362
Parameters
Conditions
Min
Typ
Max Units
POWER INTERFACE
Pin
VPOS
Supply Voltage
4.5
5
5.5
V
Quiescent Current
19
TBD
mA
vs. Temperature
-40
C
T
A
85
C
19
mA
Supply Voltage Sensitivity
TBD
TBD
TBD
mA/V
Supply Current
PWDN
enabled
TBD
A
Notes
1. Using an external 100
resistor connected between
INHI
and
INLO
to produce a net 50
input resistance.
2. Determined by linear regression.
3. The voltage required at this pin is 10x the rms value of the steady-state output of the amplifier section.
)……….………..………TBD
Equivalent Voltage …………………TBD mVrms
Internal Power Dissipation ….………...……..500 mW
*Stresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
C/W
Maximum Junction Temperature ……….…+125
C
Operating Temperature Range .…..-40
C to +85
C
Storage Temperature Range …….-65
C to +150
C
Lead Temperature Range (Soldering 60 sec)..+300
C
CAUTION
ESD
(electrostatic
discharge)
sensitive
device.
E lec trostatic
c ha rg es
as
hig h
as
4000
V
rea dily
accumulate
on
the
human
body
and
tes
t
equipm ent
a nd
c an
dis char g e
w itho ut
de tec tion.
Althoug h
the
AD836 2
features
proprietary
ESD
protection
circ uitr y,
pe rm anent
da m ag e
m ay
o cc ur
on
devices
subjected
to
high
energy
[>250
V
H
BM]
elec trosta tic
disc harg es.
T herefore,
proper
E S D
precautions
are
recommended
to
avoid
performa nc e
d eg rad atio n
or
loss
of
functiona lity.
W
A
N
G
ESD
SENSITIVE
DEVICE
ORDERING GUIDE
Model
Temp. Range
Package Description
AD8362ARU
-40
C to +85
C
Tube, 16-Lead TSSOP
AD8362ARU-REEL7
7" Tape and Reel
AD8362ARU-REEL
13" Tape and Reel
AD8362-EVAL
Evaluation Board
Rev. PrN 02/14/02
- 3 -
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage V
POS
……...…...…………… .5.5V
Input Power (re: 50
JA
…………………………………….…125
PRELIMINARY TECHNICAL DATA
AD8362
PIN CONFIGURATION
COMM
1
16
AC OM
CHPF
2
15
VR EF
DECL
3
14
VT GT
INHI
4
AD8362
TOP VIEW
(Not to Scale)
13
VPO S
INLO
5
12
VO UT
DECL
6
11
VSET
PWDN
7
10
AC OM
COMM
8
9
CLPF
Pin Function Descriptions
Pin
Name
Description
Equivalent Circuit
1, 8
COMM
Common connection. Connect via low impedance to system common.
2
CHPF
Input HPF. Connect to common via a capacitor to determine 3 dB point of input signal high-
pass filter.
3, 6
DECL
Decoupling terminals for
INHI
and
INLO
. Connect to common via a large capacitance to
complete input circuit.
4
INHI
“High” signal input terminal. Part of a differential input port with
INLO
.
5
INLO
“Low” signal input terminal. Part of a differential input port with
INHI
.
7
PWDN
Disable/Enable control input. Apply logic high voltage to shut AD8362 down.
9
CLPF
Connection for loop filter integration (averaging) capacitor, the other pin of which is usually
grounded via a resistor to improve loop stability and response time.
10, 16
ACOM
Analog common connection for output amplifier.
11
VSET
The voltage applied to this pin sets the decibel value of the required RF input voltage that
results in zero current out of pin
CLPF
and thus the loop integrating capacitor.
12
VOUT
Output of error amplifier. In measurement mode, normally connected directly to
VSET
.
13
VPOS
Connect to +5 V power supply.
14
VTGT
The logarithmic intercept voltage is proportional to the voltage applied to this pin. The use of a
lower target voltage increases the crest factor capacity.
15
VREF
General-purpose reference voltage output of 1.25V (usually connected only to
VTGT
).
Rev. PrN 02/14/02
- 4 -
PRELIMINARY TECHNICAL DATA
AD8362
Evaluation Board
Thus, the signal voltage at the output of T1 is 6 dB larger than at
its input. This is effectively the input signal magnitude which the
AD8362 measures.
Figure XX shows the schematic of the AD8362 evaluation
board. It supports operation of the AD8362 in Measurement
Modes or Controller Modes, and allows for the use of the
internally-generated reference voltage to be used as the
target voltage.
The AD8362 eval board has been designed to accommodate other
single-ended interfaces. If either of the configurations described
below are used, balun T1 may be eliminated, at the expense of a
6 dB reduction in measurement range at the high end and reduced
sensitivity to very small signals.
CH PF
signal path squarer
INHI
INLO
x
2
CLP F
Balun T1 may be removed and replaced with two resistors which
will match a 50
source to the input impedance of the AD8362.
In this case, RA should be 25
VOUT
VTGT
, as
shown in Figure X2. Note that the unused input to the AD8362
must be ac-coupled to ground, via capacitor C5 and the 0
and RB should be 33
x
2
differential
amplifier
extern al
feedback
path
reference
squarer
external
connection
VSET
resistor RC. In this configuration, R16 is open.
AD8362
R14
BIAS
VPOS
R15
VREF
1
16
C8
2
15
CO MM
PWDN
RA
25
C7
C10
3
14
C6
RFIN
Figure X4 Simplified Block Diagram in Measurement Mode
4
13
RB
33
5
12
Figure X4 shows the AD8362 as it could be configured for
measurement mode operation. The AD8362 compares an
amplified, squared, averaged version of the input signal to a
target voltage which has been applied to an identical
squaring cell. These voltages are applied to a differential
amplifier, the output of which is fed back in Measurement
Mode to the gain control of the input variable attenuator.
This forces the output of the signal-path squaring cell to be
equal to the output of the reference squaring cell. In this
mode, the output voltage of the differential amplifier is a
linear-in-dB representation of the input signal rms voltage.
C5
RC
0
6
11
C4
7
10
8
9
Figure X2 Single-ended Drive Without a Balun – Option A
Alternatively, T1 may be removed, a 0
resistor installed at
positions RA
and RC and a 100
resistor installed at R16, as
shown in Figure X3.
Input Circuit
R14
The input to the AD8362 is differential in order to optimize
the input measurement range, among other things. A balun
can transform a single-ended RF signal to differential form.
The ETC1.6-4-2-3, 500 MHz – 2.5 GHz, 4:1 balun is
installed on the evaluation board. Note that the RF input
impedance at the RFIN connector may not be 50
R15
1
16
C8
2
15
RA
0
C7
C10
3
14
RFIN
C6
4
13
unless a
balun having the correct ratio is used. If the AD8362 is to be
evaluated at frequencies higher than 2.5 GHz or lower than
500 MHz, better performance will be obtained if this balun is
replaced with one that is designed for those frequencies.
RC
0
R16 100
5
12
C5
6
11
C4
7
10
8
9
It is important to note that the balun transformer steps up the
signal voltage by the square root of its turns ratio.
Figure X3 Single ended Drive without a Balun – Option B
Rev. PrN 02/14/02
- 5 -
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