ADG726 32 prd

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PRELIMINARY TECHNICAL DATA
ΩΩ
1.8 V to 5.5 V, ±2.5 V, Analog Multiplexers
16-/32- Channel, 3.5
ΩΩ
Preliminary Technical Data
ADG726/ADG732
FEATURES
1.8 V to 5.5 V Single Supply
±2.5 V Dual Supply Operation
3.5
FUNCTIONAL BLOCK DIAGRAMS
On Resistance
ADG732
ADG726
On Resistance Flatness
Rail to Rail Operation
30ns Switching Times
Single 32 to 1 Channel Multiplexer
Dual/Differential 16 to 1 Channel Multiplexer
TTL/CMOS Compatible Inputs
For Functionally Equivalent devices with Serial Interface
See ADG725/ADG731
S1
S1A
DA
S16A
D
S1B
DB
S32
S16B
APPLICATIONS
Optical Applications
Data Acquisition Systems
Communication Systems
Relay replacement
Audio and Video Switching
Battery Powered Systems
Medical Instrumentation
Automatic Test Equipment
WR
1 OF 32
DECODER
WR
CSA
1 OF 16
DECODER
CS
CSB
A0
A1
A2 A4
EN
A0
A1
A2
A3
EN
GENERAL DESCRIPTION
The ADG726/ADG732 are monolithic CMOS 32
channel/dual 16 channel analog multiplexers. The
ADG732 switches one of thirty-two inputs (S1-S32) to a
common output, D, as determined by the 5-bit binary
address lines A0, A1, A2, A3 and A4. The ADG726
switches one of sixteen inputs as determined by the four
bit binary address lines, A0, A1, A2 and A3.
On chip latches facilitate microprocessor interfacing. The
ADG726 device may also be configured for differential
operation by tying CSA and CSB together. An
input
is used to enable or disable the devices. When disabled, all
channels are switched OFF.
These multiplexers are designed on an enhanced submi-
cron process that provides low power dissipation yet gives
high switching speed, very low on resistance and leakage
currents. They operate from single supply of 1.8V to 5.5V
and ±2.5 V dual supply, making them ideally suited to a
variety of applications. On resistance is in the region of a
few Ohms and is closely matched between switches and
very flat over the full signal range. These parts can operate
equally well as either Multiplexers or De-Multiplexers
and have an input signal range which extends to the sup-
plies. In the OFF condition, signal levels up to the
supplies are blocked. All channels exhibit break before
make switching action preventing momentary shorting
when switching channels.
They are available in either 48 lead LFCSP or TQFP
package.
PRODUCT HIGHLIGHTS
1. +1.8 V to +5.5 V Single or ±2.5 V Dual Supply
operation. These parts are specified and guaranteed
with +5 V ±10%, +3 V ±10% single supply and
±2.5 V ±10% dual supply rails.
2. On Resistance of 3.5 Ω .
3. Guaranteed Break-Before-Make Switching Action.
4. 7mm x 7mm 48 lead LF Chip Scale Package (CSP)
or 48 lead TQFP package.
REV. PrD 2001
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 2001
0.5
A3
PRELIMINARY TECHNICAL DATA
ADG726/ADG732–SPECIFICATIONS
1
(V
DD
= 5V ± 10%, V
SS
= 0V, GND = 0 V, unless otherwise noted)
B Version
–40°C
Parameter
+25
o
C
to +85°C
Units Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
0 V to V
DD
V
On-Resistance (R
ON
)
3.5
typ
V
S
= 0 V to V
DD
, I
DS
= 10 mA;
5.5
6
max
Test Circuit 1
On-Resistance Match Between
0.3
typ
V
S
= 0 V to V
DD
, I
DS
= 10 mA
Channels (
R
ON
)
0.8
max
On-Resistance Flatness (R
FLAT(ON)
)
0.5
typ
V
S
= 0 V to V
DD
, I
DS
= 10 mA
1.2
max
LEAKAGE CURRENTS
V
DD
= 5.5 V
Source OFF Leakage I
S
(OFF)
±0.01
nA typ
V
D
= 4.5 V/1 V, V
S
= 1 V/4.5 V;
±0.5
±5
nA max
Test Circuit 2
Drain OFF Leakage I
D
(OFF)
±0.01
nA typ
V
D
= 4.5 V/1 V, V
S
= 1 V/4.5 V;
±0.5
±5
nA max
Test Circuit 3
Channel ON Leakage I
D
, I
S
(ON)
±0.01
nA typ
V
D
= V
S
= 1 V, or 4.5V;
± 1
±10
nA max
Test Circuit 4
DIGITAL INPUTS
Input High Voltage, V
INH
2.4
V min
Input Low Voltage, V
INL
0.8
V max
Input Current
I
INL
or I
INH
0.005
µA typ
V
IN
= V
INL
or V
INH
±0.1
µA max
C
IN
, Digital Input Capacitance
5
pF typ
DYNAMIC CHARACTERISTICS
2
t
TRANSITION
40
ns typ
R
L
= 300
, C
L
= 35 pF,Test Circuit 5;
60
ns max
V
S1
= 3 V/0 V, V
S32
= 0 V/3V
Break-Before-Make Time Delay, t
D
30
ns typ
R
L
= 300
, C
L
= 35 pF;
1
ns min
V
S
= 3 V, Test Circuit 6
t
ON
(EN,
)
32
ns typ
R
L
= 300
, C
L
= 35 pF;
50
ns max
V
S
= 3 V, Test Circuit 7
t
OFF
(EN)
10
ns typ
R
L
= 300
, C
L
= 35 pF;
14
ns max
V
S
= 3 V, Test Circuit 8
Charge Injection
± 5
pC typ
V
S
= 0 V, R
S
= 0
, C
L
= 1 nF;
Test Circuit 9
Off Isolation
-60
dB typ
, C
L
= 5 pF, f = 100 kHz;
Test Circuit 10
Channel to Channel Crosstalk
-60
dB typ
, C
L
= 5 pF, f = 100 kHz;
Test Circuit 11
-3 dB Bandwidth
10
MHz typ R
L
= 50
, C
L
= 5 pF, Test Circuit 10
C
S
(OFF)
13
pF typ
f = 1 MHz
C
D
(OFF)
ADG726
180
pF typ
f = 1 MHz
ADG732
360
pF typ
f = 1 MHz
C
D
, C
S
(ON)
ADG726
200
pF typ
f = 1 MHz
ADG732
400
pF typ
f = 1 MHz
POWER REQUIREMENTS
V
DD
= +5.5 V
I
DD
10
µA typ
Digital Inputs = 0 V or +5.5 V
20
µA max
NOTES
1
Temperature range is as follows: B Version: –40°C to +85°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
–2–
REV. PrD
R
L
= 50
R
L
= 50
PRELIMINARY TECHNICAL DATA
SPECIFICATIONS
1
ADG726/ADG732
(V
DD
= 3V ± 10%, V
SS
= 0V, GND = 0 V, unless otherwise noted)
B Version
–40°C
Parameter
+25
o
C
to +85°C
Units Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
0 V to V
DD
V
On-Resistance (R
ON
)
6
typ
V
S
= 0 V to V
DD
, I
DS
= 10 mA;
11
12
max
Test Circuit 1
On-Resistance Match Between
0.4
typ
V
S
= 0 V to V
DD
, I
DS
= 10 mA
Channels (
R
ON
)
1.2
max
On-Resistance Flatness (R
FLAT(ON)
)
3
max
V
S
= 0 V to V
DD
, I
DS
= 10 mA
LEAKAGE CURRENTS
V
DD
= 3.3 V
Source OFF Leakage I
S
(OFF)
±0.01
nA typ
V
S
= 3 V/1 V, V
D
= 1 V/3 V;
± 1
± 5
nA max
Test Circuit 2
Drain OFF Leakage I
D
(OFF)
±0.01
nA typ
V
S
= 1 V/3 V, V
D
= 3 V/1 V;
± 1
± 5
nA max
Test Circuit 3
Channel ON Leakage I
D
, I
S
(ON)
±0.01
nA typ
V
S
= V
D
= +1 V or +3 V;
± 1
±10
nA max
Test Circuit 4
DIGITAL INPUTS
Input High Voltage, V
INH
2.0
V min
Input Low Voltage, V
INL
0.8
V max
Input Current
I
INL
or I
INH
0.005
µA typ
V
IN
= V
INL
or V
INH
±0.1
µA max
C
IN
, Digital Input Capacitance
5
pF typ
DYNAMIC CHARACTERISTICS
2
t
TRANSITION
45
ns typ
R
L
= 300
, C
L
= 35 pF Test Circuit 5
75
ns max
V
S1
= 2 V/0 V, V
S32
= 0 V/2 V
Break-Before-Make Time Delay, t
D
30
ns typ
R
L
= 300
, C
L
= 35 pF;
1
ns min
V
S
= 2 V, Test Circuit 6
t
ON
(EN,
)
40
ns typ
R
L
= 300
, C
L
= 35 pF;
70
ns max
V
S
= 2 V, Test Circuit 7
t
OFF
(EN)
20
ns typ
R
L
= 300
, C
L
= 35 pF;
28
ns max
V
S
= 2 V, Test Circuit 8
Charge Injection
± 5
pC typ
V
S
= 0 V, R
S
= 0
, C
L
= 1 nF;
Test Circuit 9
Off Isolation
-60
dB typ
, C
L
= 5 pF, f = 1 MHz;
Test Circuit 10
Channel to Channel Crosstalk
-60
dB typ
, C
L
= 5 pF, f = 1 MHz;
Test Circuit 11
-3 dB Bandwidth
10
MHz typ
R
L
= 50
, C
L
= 5 pF, Test Circuit 10
C
S
(OFF)
13
pF typ
f = 1 MHz
C
D
(OFF)
ADG726
180
pF typ
f = 1 MHz
ADG732
360
pF typ
f = 1 MHz
C
D
, C
S
(ON)
ADG726
200
pF typ
f = 1 MHz
ADG732
400
pF typ
f = 1 MHz
POWER REQUIREMENTS
V
DD
= +3.3 V
I
DD
10
µA typ
Digital Inputs = 0 V or +3.3 V
20
µA max
NOTES
1
Temperature ranges are as follows: B Version: –40°C to +85°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
REV. PrD
–3–
R
L
= 50
R
L
= 50
PRELIMINARY TECHNICAL DATA
ADG726/ADG732–SPECIFICATIONS
1
Dual Supply
B Version
–40°C
Parameter
+25
o
C
to +85°C
Units Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
V
SS
to V
DD
V
On-Resistance (R
ON
)
3.5
typ
V
S
= V
SS
to V
DD
, I
DS
= 10 mA;
5.5
6
max
Test Circuit 1
On-Resistance Match Between
0.3
typ
V
S
= V
SS
to V
DD
, I
DS
= 10 mA
Channels (
R
ON
)
0.8
max
On-Resistance Flatness (R
FLAT(ON)
)
0.5
typ
V
S
= V
SS
to V
DD
, I
DS
= 10 mA
1.2
max
LEAKAGE CURRENTS
V
DD
= +2.75 V, V
SS
= -2.75 V
Source OFF Leakage I
S
(OFF)
±0.01
nA typ
V
S
= +2.25 V/-1.25 V, V
D
= -1.25 V/+2.25 V;
± 1
± 5
nA max
Test Circuit 2
Drain OFF Leakage I
D
(OFF)
±0.01
nA typ
V
S
= +2.25 V/-1.25 V, V
D
= -1.25 V/+2.25 V;
± 1
± 5
nA max
Test Circuit 3
Channel ON Leakage I
D
, I
S
(ON)
±0.01
nA typ
V
S
= V
D
= +2.25 V/-1.25 V, Test Circuit 4
± 1
±10
nA max
DIGITAL INPUTS
Input High Voltage, V
INH
1.7
V min
Input Low Voltage, V
INL
0.7
V max
Input Current
I
INL
or I
INH
0.005
µA typ
V
IN
= V
INL
or V
INH
±0.1
µA max
C
IN
, Digital Input Capacitance
5
pF typ
DYNAMIC CHARACTERISTICS
2
t
TRANSITION
40
ns typ
R
L
= 300
, C
L
= 35 pF Test Circuit 5
60
ns max
V
S1
= 1.5 V/0 V,V
S32
= 0 V/1.5 V
Break-Before-Make Time Delay, t
D
15
ns typ
R
L
= 300
, C
L
= 35 pF;
1
ns min
V
S
= 1.5 V, Test Circuit 6
t
ON
(EN,
)
32
ns typ
R
L
= 300
, C
L
= 35 pF;
50
ns max
V
S
= 1.5 V, Test Circuit 7
t
OFF
(EN)
16
ns typ
R
L
= 300
, C
L
= 35 pF;
26
ns max
V
S
= 1.5 V, Test Circuit 8
Charge Injection
± 8
pC typ
V
S
= 0 V, R
S
= 0
, C
L
= 1 nF; Test 9
Off Isolation
-60
dB typ
, C
L
= 5 pF, f = 1 MHz;
Test Circuit 10
Channel to Channel Crosstalk
-60
dB typ
, C
L
= 5 pF, f = 1 MHz;
Test Circuit 11
-3 dB Bandwidth
10
MHz typ R
L
= 50
, C
L
= 5 pF, Test Circuit 10
C
S
(OFF)
13
pF typ
C
D
(OFF)
ADG726
180
pF typ
f = 1 MHz
ADG732
360
pF typ
f = 1 MHz
C
D
, C
S
(ON)
ADG726
200
pF typ
f = 1 MHz
ADG732
400
pF typ
f = 1 MHz
POWER REQUIREMENTS
V
DD
= +2.75 V
I
DD
10
µA typ
Digital Inputs = 0 V or +2.75 V
20
µA max
I
SS
10
µA typ
V
SS
= -2.75 V
20
µA max
Digital Inputs = 0 V or +2.75 V
NOTES
1
Temperature range is as follows: B Version: –40°C to +85°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
–4–
REV. PrD
(V
DD
= +2.5 V ±10%, V
SS
= -2.5 V ±10%, GND = 0 V, unless otherwise noted)
R
L
= 50
R
L
= 50
PRELIMINARY TECHNICAL DATA
ADG726/ADG732
TIMING CHARACTERISTICS
1,2, 3
Parameter
Limit at T
MIN
, T
MAX
Units
Conditions/Comments
t
1
0
ns min
to
Setup Time
t
2
0
ns min
to
Hold Time
t
3
20
ns min
pulse width
t
4
10
ns min
Time between
cycles
t
5
5
ns min
Address, Enable Setup Time
t
6
2
ns min
Address, Enable Hold Time
NOTES
1
See Figure 1.
2
All input signals are specified with tr =tf = 5ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
3
Guaranteed by design and characterisation, not production tested.
Specifications subject to change without notice.
CS
t
1
t
3
t
2
t
4
WR
t
5
t
6
A0, A1
, A
2, A3, (A4)
EN
Figure 1. Timing Diagram
Figure 1 shows the timing sequence for latching the switch address and enable inputs. The latches are level sensitive;
therefore, while
is held low, the latches are transparent and the switches respond to the address and enable inputs.
This input data is latched on the rising edge of
. The ADG726 has two
inputs. This enables the part to be used
either as a dual 16-1 channel multiplexer or a differential 16 channel multiplexer. If a differential output is required, tie
and
together.
REV. PrD
–5–
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