AD6623 0

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a
4-Channel, 104 MSPS Digital
Transmit Signal Processor (TSP)
AD6623
FEATURES
Pin Compatible to the AD6622
18-Bit Parallel Digital IF Output
Real or Interleaved Complex
18-Bit Bidirectional Parallel Digital IF Input/Output
Allows Cascade of Chips for Additional Channels
Clipped or Wrapped Over Range
Two’s Complement or Offset Binary Output
Four Independent Digital Transmitters in Single Package
RAM Coefficient Filter (RCF)
Programmable IF and Modulation for Each Channel
Programmable Interpolating RAM Coefficient Filter
p/4-DQPSK Differential Phase Encoder
3p/8-PSK Linear Encoder
8-PSK Linear Encoder
Programmable GMSK Look-Up Table
Programmable QPSK Look-Up Table
All-Pass Phase Equalizer
Programmable Fine Scaler
Programmable Power Ramp Unit
High Speed CIC Interpolating Filter
Digital Resampling for Noninteger Interpolation Rates
NCO Frequency Translation
Spurious Performance Better than –100 dBc
Separate 3-Wire Serial Data Input for Each Channel
Bidirectional Serial Clocks and Frames
Microprocessor Control
2.5 V CMOS Core, 3.3 V Outputs, 5 V Inputs
JTAG Boundary Scan
APPLICATIONS
Cellular/PCS Base Stations
Micro/Pico Cell Base Stations
Wireless Local Loop Base Stations
Multicarrier, Multimode Digital Transmit
GSM, EDGE, IS136, PHS, IS95, TDS CDMA, UMTS,
CDMA2000
Phased Array Beam Forming Antennas
Software Defined Radio
Tuning Resolution Better than 0.025 Hz
Real or Complex Outputs
FUNCTIONAL BLOCK DIAGRAM
NCO = NUMERICALLY CONTROLLED
OSCILLATOR/TUNER
SDINA
SDFIA
SDFOA
SCLKA
DATA
RAM
COEFFICIENT
FILTER
I
Q
SCALER
AND
POWER
RAMP
I
Q
CIC5
FILTER
I
Q
RCIC2
FILTER
I
Q
CHAN
A
QIN
SP
ORT
NCO
IN
[17–0]
SDINB
SDFIB
SDFOB
SCLKB
DATA
RAM
COEFFICIENT
FILTER
I
Q
SCALER
AND
POWER
RAMP
I
Q
CIC5
FILTER
I
Q
RCIC2
FILTER
I
Q
CHAN B
SP
ORT
NCO
SYNC
4
SUMMATION
SDINC
SDFIC
SDFOC
SCLKC
SP
ORT
DATA
RAM
COEFFICIENT
FILTER
I
Q
SCALER
AND
POWER
RAMP
I
Q
CIC5
FILTER
I
Q
RCIC2
FILTER
I
Q
NCO
CHAN C
OEN
SDIND
SDFID
DATA
RAM
COEFFICIENT
FILTER
I
Q
SCALER
AND
POWER
RAMP
I
Q
CIC5
FILTER
I
Q
RCIC2
FILTER
I
Q
CHAN D
QOUT
OUT
[17:0]
SP
ORT
NCO
SDFOD
SCLKD
JTAG
MICROPORT
TDL
TDO
TMS TCK TRST
D[7:0]
DS
DTACK
RW
MODE
A[2:0]
CS
CLK RESET
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
 AD6623
TABLE OF CONTENTS
APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
PRODUCT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . 4
LOGIC INPUTS (5 V TOLERANT) . . . . . . . . . . . . . . . . . . . . . . . . . 4
LOGIC OUTPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
IDD SUPPLY CURRENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
POWER DISSIPATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
MICROPROCESSOR PORT, MODE INM (MODE = 0) . . . . . . . . . 6
MICROPROCESSOR PORT, MOTOROLA (MODE = 1) . . . . . . . . 6
THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
EXPLANATION OF TEST LEVELS . . . . . . . . . . . . . . . . . . . . . . . . . . 10
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
ESD SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
POWER SUPPLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
INPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
MICROPORT CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
OUTPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
JTAG AND BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Serial Master Mode (SCS = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Serial Slave Mode (SCS = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Self-Framing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
External Framing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Serial Port Cascade Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Serial Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
OVERVIEW OF THE RCF BLOCKS . . . . . . . . . . . . . . . . . . . . . . . . 16
PSK MODULATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8-PSK MODULATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3
/8-8-PSK MODULATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
MSK Look-Up Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
GMSK Look-Up Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
QPSK Look-Up Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
PHASE EQUALIZER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
SCALE AND RAMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
RCF POWER RAMPING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
CASCADED INTERGRATOR COMB (CIC)
INTERPOLATING FILTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
CIC5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
NUMERICALLY CONTROLLED
Phase Dither . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Amplitude Dither . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Phase Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
NCO Frequency Update and Phase Offset Update
Hold-Off Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
NCO Control Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Start with Soft Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Hop with Soft Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Hop with Pin Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Beam with Soft Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Beam with Pin Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
SCALING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Multicarrier Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Single Carrier Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
MicroPort Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
EXTERNAL MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Motorola Nonmultiplexed Mode (MNM) . . . . . . . . . . . . . . . . . . . . . 30
External Address 7 Upper Address Register (UAR) . . . . . . . . . . . . . . 30
External Address 6 Lower Address Register (LAR) . . . . . . . . . . . . . . 30
External Address 5 Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
External Address 4 Sleep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
External Address 3:0 (Data Bytes) . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
AD6623 and AD6622 Compatibility
Common Function Registers (not associated
with a particular channel) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Channel Function Registers (0x1XX = Ch. A,
0x2XX = Ch. B, 0x3XX = Ch. C, 0x4XX = Ch. D) . . . . . . . . . . . 31
(0x001) Sync Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
(0x002) BIST Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
(0x003) BIST Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Channel Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
(0xn00) Start Update Hold-Off Counter . . . . . . . . . . . . . . . . . . . . . . 34
(0xn01) NCO Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
(0xn02) NCO Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
(0xn03) NCO Frequency Update Hold-Off Counter . . . . . . . . . . . . . 34
(0xn04) NCO Phase Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
(0xn05) NCO Phase Offset Update Hold-Off Counter . . . . . . . . . . . . 34
(0xn06) CIC Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
(0xn07) CIC2 Decimation – 1 (M
CIC2
– 1) . . . . . . . . . . . . . . . . . . . . . 34
(0xn09) CIC5 Interpolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
(0xn0A) Number of RCF Coefficients – 1 . . . . . . . . . . . . . . . . . . . . . 34
(0xn0B) RCF Coefficient Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
(0xn0C) Channel Mode Control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
(0xn0E) Fine Scale Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
(0xn0F) RCF Time Slot Hold-Off Counter . . . . . . . . . . . . . . . . . . . . 35
(0xn10–0xn11) RCF Phase Equalizer Coefficients . . . . . . . . . . . . . . . 35
(0xn12–0xn15) FIR-PSK Magnitudes . . . . . . . . . . . . . . . . . . . . . . . . 35
(0xn16) Serial Port Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
(0xn17) Power Ramp Length 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
(0xn18) Power Ramp Length 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
(0xn19) Power Ramp Rest Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
(0xn20–0xn1F) Unused . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
(0xn20–0xn3F) Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
(0xn40–0xn17F) Power Ramp Coefficient Memory . . . . . . . . . . . . . . 35
Pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Write Pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Read Pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
USING THE AD6623 TO PROCESS UMTS CARRIERS . . . . . . . . 36
DIGITAL-TO-ANALOG CONVERTER (DAC) SELECTION . . . . . . . 36
MULTIPLE TSP OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Determining the Number of TSPs to Use . . . . . . . . . . . . . . . . . . . . 36
Driving Multiple TSP Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . 37
–2–
REV. 0
AD6623
PRODUCT DESCRIPTION
The AD6623 is a 4-channel Transmit Signal Processor (TSP)
that creates high bandwidth data for Transmit Digital-to-Analog
Converters (TxDACs) from baseband data provided by a Digital
Signal Processor (DSP). Modern TxDACs have achieved suffi-
ciently high sampling rates, analog bandwidth, and dynamic range
to create the first Intermediate Frequency (IF) directly. The
AD6623 synthesizes multicarrier and multistandard digital signals
to drive these TxDACs. The RAM-based architecture allows easy
reconfiguration for multimode applications. Modulation, pulse-
shaping and anti-imaging filters, static equalization, and tuning
functions are combined in a single, cost-effective device. Digital
IF signal processing provides repeatable manufacturing, higher
accuracy, and more flexibility than comparable high dynamic
range analog designs.
The AD6623 has four identical digital TSPs complete with synchro-
nization circuitry and cascadable wideband channel summation.
AD6623 is pin compatible to AD6622 and can operate in AD6622-
compatible control register mode.
The AD6623 utilizes a 3.3 V I/O power supply and a 2.5 V core
power supply. All I/O pins are 5 V tolerant. All control registers
and coefficient values are programmed through a generic micro-
processor interface. Intel and Motorola microprocessor bus modes
are supported. All inputs and outputs are LVCMOS compatible.
INOUT[17:0] can alternatively be masked off by software to
allow preceding AD6623’s outputs to be ignored.
Each channel accepts input data from independent serial ports
that may be connected directly to the serial port of Digital Signal
Processor (DSP) chips.
The RCF implements any one of the following functions:
Interpolating Finite Impulse Response (FIR) filter,
/4-DQPSK
modulator, 8-PSK modulator, or 3
/8-8-PSK modulator, GMSK
modulator, and QPSK modulator. Each AD6623 channel can
be dynamically switched between the GMSK modulation mode
and the 3
/8-8-PSK modulation mode in order to support the
GSM/EDGE standard. The RCF also implements an Allpass
Phase Equalizer (APE) which meets the requirements of IS-95-A/B
standard (CDMA transmission).
The programmable Scale and Power Ramp block allows power
ramping on a time-slot basis as specified for some air-interface
standards (e.g., GSM, EDGE). A fine scaling unit at the pro-
grammable FIR filter output allows an easy signal amplitude
level adjustment on time slot basis.
The CIC5 provides integer rate interpolation from 1 to 32 and
coarse anti-image filtering. The rCIC2 provides fractional rate
interpolation from 1 to 4096 in steps of 1/512. The wide range
of interpolation factors in each CIC filter stage and a highly
flexible resampler incorporated into rCIC2 makes the AD6623
useful for creating both narrowband and wideband carriers in a
high-speed sample stream.
The high resolution 32-bit NCO allows flexibility in frequency
planning and supports both digital and analog air interface stan-
dards. The high speed NCO tunes the interpolated complex signal
from the rCIC2 to an IF channel. The result may be real or com-
plex. Multicarrier phase synchronization pins and phase offset
registers allow intelligent management of the relative phase of
independent RF channels. This capability supports the require-
ments for phased array antenna architectures and management
of the wideband peak/power ratio to minimize clipping at the DAC.
The wideband Output Ports can deliver real or complex data.
Complex words are interleaved into real (I) and imaginary (Q)
parts at half the master clock rate.
FUNCTIONAL OVERVIEW
Each TSP has five cascaded signal processing elements: a pro-
grammable interpolating RAM Coefficient Filter (RCF), a
programmable Scale and Power Ramp, a programmable fifth order
Cascaded Integrator Comb (CIC5) interpolating filter, a flexible
second order Resampling Cascaded Integrator Comb filter (rCIC2),
and a Numerically Controlled Oscillator/Tuner (NCO).
The outputs of the four TSPs are summed and scaled on-chip.
In multicarrier wideband transmitters, a bidirectional bus allows
the Parallel (wideband) IF Input/Output to drive a second DAC.
In this operational mode two AD6623 channels drive one DAC
and the other two AD6623 channels drive a second DAC. Mul-
tiple AD6623s may be combined by driving the INOUT[17:0] of
the succeeding with the OUT[17:0] of the preceding chip. The
REV. 0
–3–
  AD6623
RECOMMENDED OPERATING CONDITIONS
Test
AD6623
Parameter
Level
Min
Typ
Max
Unit
VDD
IV
2.25
2.5
2.75
V
VDDIO
IV
3.0
3.3
3.6
V
T
AMBIENT
IV
–40
+25
+70
°C
ELECTRICAL CHARACTERISTICS
Parameter (Conditions)
Temp
Test Level
Min
Typ
Max
Unit
LOGIC INPUTS (5 V TOLERANT)
Logic Compatibility
Full
3.3 V CMOS
Logic “1” Voltage
Full
IV
2.0
5.0
V
Logic “0” Voltage
Full
IV
–0.3
+0.8
V
Logic “1” Current
Full
IV
1
10
µ
A
Logic “0” Current
Full
IV
0
10
µ
A
Input Capacitance
25
°
C
V
4
pF
LOGIC OUTPUTS
Logic Compatibility
Full
3.3 V CMOS/TTL
Logic “1” Voltage (I
OH
= 0.25 mA)
Full
IV
2.0
VDD – 0.2
V
Logic “0” Voltage (I
OL
= 0.25 mA)
Full
IV
0.2
0.4
V
IDD SUPPLY CURRENT
CLK = 104 MHz, VDD = 2.75 V
*
Full
IV
422
TBD
*
mA
CLK = 104 MHz, VDDIO = 3.6 V
*
Full
IV
193
mA
GSM Example: CORE
V
232
mA
I/O
56
mA
IS-136 Example: CORE
V
207
mA
I/O
55
mA
WBCDMA Example
V
Tbd
mA
Sleep Mode
Full
IV
Tbd
TBD
mA
POWER DISSIPATION
GSM Example
V
740
mW
IS-136 Example
V
700
mW
WBCDMA Example
V
Tbd
mW
Sleep Mode
Full
IV
Tbd
TBD
mW
*
This specification denotes an absolute maximum supply current for the device. The conditions include all channels active, minimum interpolation in both CIC
stages, and maximum switching of input data. In an actual application the power will be less.
See the Thermal Management section of the data sheet for further details.
–4–
REV. 0
 AD6623
GENERAL TIMING CHARACTERISTICS
1, 2
Test
AD6623AS
Parameter (Conditions)
Temp
Level
Min
Typ
Max
Unit
CLK Timing Requirements:
t
CLK
CLK Period
Full
I
9.6
ns
t
CLKL
CLK Width Low
Full
IV
3
ns
t
CLKH
CLK Width High
Full
IV
3
0.5 × t
CLK
ns
RESET
Timing Requirement:
t
RESL
RESET
Width Low
Full
I
30.0
ns
Input Data Timing Requirements:
t
SI
INOUT[17:0], QIN to ↑CLK Setup Time
Full
IV
1
ns
t
HI
INOUT[17:0], QIN to ↑CLK Hold Time
Full
IV
2
ns
Output Data Timing Characteristics:
t
DO
↑CLK to OUT[17:0], INOUT[17:0],
QOUT Output Delay Time
Full
IV
2
6
ns
t
DZO
OEN HIGH to OUT[17:0] Active
Full
IV
3
7.5
ns
SYNC Timing Requirements:
t
SS
SYNC(0, 1, 2, 3) to
↑
CLK Setup Time
Full
IV
1
ns
t
HS
SYNC(0, 1, 2, 3) to
↑
CLK Hold Time
Full
IV
2
ns
Master Mode Serial Port Timing Requirements (SCS = 0):
Switching Characteristics
3
t
DSCLK1
↑CLK to ↑SCLK Delay (divide by 1)
Full
IV
4
10.5
ns
t
DSCLKH
↑CLK to ↑SCLK Delay (for any other divisor) Full
IV
5
13
ns
t
DSCLKL
↑CLK to ↓SCLK Delay
(divide by 2 or even number)
Full
IV
3.5
9
ns
t
DSCLKLL
↓CLK to ↓SCLK Delay
(divide by 3 or odd number)
Full
IV
4
10
ns
Channel is Self-Framing
t
SSDI0
SDIN to ↑SCLK Setup Time
Full
IV
1.7
ns
t
HSDI0
SDIN to ↑SCLK Hold Time
Full
IV
0
ns
t
DSFO0A
↑SCLK to SDFO Delay
Full
IV
0.5
3.5
ns
Channel is External-Framing
t
SSFI0
SDFI to ↑SCLK Setup Time
Full
IV
2
ns
t
HSFI0
SDFI to ↑SCLK Hold Time
Full
IV
0
ns
t
SSDI0
SDIN to ↑SCLK Setup Time
Full
IV
2
ns
t
HSDI0
SDIN to ↑SCLK Hold Time
Full
IV
0
ns
t
DSFO0B
↑SCLK to SDFO Delay
Full
IV
0.5
3
ns
Slave Mode Serial Port Timing Requirements (SCS = 1):
Switching Characteristics
3
t
SCLK
SCLK Period
Full
IV
2
t
CLK
ns
t
SCLKL
SCLK Low Time
Full
IV
3.5
ns
t
SCLKH
SCLK High Time
Full
IV
3.5
ns
Channel is Self-Framing
t
SSDH
SDIN to
↑
SCLK Setup Time
Full
IV
1
ns
t
HSDH
SDIN to
↑
SCLK Hold Time
Full
IV
2.5
ns
t
DSFO1
↑
SCLK to SDFO Delay
Full
IV
4
10
ns
Channel is External-Framing
t
SSFI1
SDFI to
↑
SCLK Setup Time
Full
IV
2
ns
t
HSFI1
SDFI to
↑
SCLK Hold Time
Full
IV
1
ns
t
SSDI1
SDIN to
↑
SCLK Setup Time
Full
IV
1
ns
t
HSDI1
SDIN to
↑
SCLK Hold Time
Full
IV
2.5
ns
t
DSFO1
↓
SCLK to SDFO Delay
Full
IV
10
ns
NOTES
1
All Timing Specifications valid over VDD range of 2.375 V to 2.675 V and VDDIO range of 3.0 V to 3.6 V.
2
C
LOAD
= 40 pF on all outputs (unless otherwise specified).
3
The timing parameters for SCLK, SDIN, SDFI, SDFO, and SYNC apply to all four channels (A, B, C, and D).
Specifications subject to change without notice.
REV. 0
–5–
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