AD7782 0

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a
Read Only, Pin Configured
24-Bit
-
ADC
AD7782
FEATURES
2-Channel, 24-Bit
-
ADC
Pin Configurable (No Programmable Registers)
Pin Selectable Input Channels
Pin Programmable Input Ranges (
2.56 V or
160 mV)
Fixed 19.79 Hz Update Rate
Simultaneous 50 Hz and 60 Hz Rejection
24-Bit No Missing Codes
18.5-Bit p-p Resolution (
2.56 V Range)
16.5-Bit p-p Resolution (
160 mV Range)
FUNCTIONAL BLOCK DIAGRAM
V
DD
GND
REFIN(+)
REFIN(–)
XTAL1 XTAL2
AD7782
OSCILLATOR
AND
PLL
AIN1(+)
AIN1(–)
AIN2(+)
AIN2(–)
MUX
BUF
PGA
24-BIT
ADC
-
SERIAL
INTERFACE
AND
CONTROL
LOGIC
DOUT/RDY
SCLK
MODE
INTERFACE
Master or Slave Mode of Operation
Slave Mode
3-Wire Serial
SPIâ„¢, QSPIâ„¢, MICROWIREâ„¢, and DSP-Compatible
Schmitt Trigger on SCLK
CS
CH1/CH2
RANGE
POWER
Specified for Single 3 V and 5 V Operation
Normal: 1.3 mA @ 3 V
Power-Down: 9
A
BASIC CONNECTION DIAGRAM
POWER SUPPLY
ON-CHIP FUNCTIONS
Rail-Rail Input Buffer and PGA
V
DD
AD7782
APPLICATIONS
Sensor Measurement
Industrial Process Control
Temperature Measurement
Pressure Measurements
Weigh Scales
Portable Instrumentation
ANALOG
INPUT
AIN1(+)
CS
AIN1(–)
DIGITAL
INTERFACE
DOUT/RDY
ANALOG
INPUT
AIN2(+)
SCLK
AIN2(–)
XTAL1
32.768kHz
CRYSTAL
REFERENCE
INPUT
REFIN(+)
REFIN(–)
XTAL2
GND
GENERAL DESCRIPTION
The AD7782 is a complete analog front end for low-frequency
measurement applications. The 24-bit sigma-delta ADC contains
two fully differential analog input channels that can be config-
ured with a gain of 1 or 16 allowing full-scale input signal ranges
of ± 2.56 V or ± 160 mV from a +2.5 V differential reference
input.
The AD7782 has an extremely simple, read-only digital interface
which can be operated in master mode or slave mode. There are
no on-chip registers to be programmed. The input signal range
and input channel selection are configured using two external pins.
The device operates from a 32.768 kHz crystal with an on-chip PLL
generating the required internal operating frequency. The output
data rate from the part is fixed via the master clock at 19.79 Hz and
provides simultaneous 50 Hz and 60 Hz rejection at this update
rate. Eighteen-bit p-p resolution can be obtained at this update rate.
The part operates from a single 3 V or 5 V supply. When operating
from 3 V supplies, the power dissipation for the part is 3.9 mW.
The AD7782 is available in a 16-lead TSSOP package.
Another part in the AD778x family is the AD7783. It is similar
to the AD7782 except it has two integrated current sources and
only one differential input channel.
SPI and QSPI are trademarks of Motorola Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
AD7782–SPECIFICATIONS
(V
DD
= 2.7 V to 3.6 V or 4.75 V to 5.25 V, REFIN(+) = 2.5 V; REFIN(–) = GND; GND = 0 V;
XTAL1/XTAL2 = 32.768 kHz Crystal; all specifications T
MIN
to T
MAX
unless otherwise noted.)
Parameter
AD7782B
Unit
Test Conditions
ADC CHANNEL SPECIFICATION
Output Update Rate
19.79
Hz nom
ADC CHANNEL
No Missing Codes
2
24
Bits min
Resolution
16
Bits p-p
±
160 mV Range, RANGE = 0
18
Bits p-p
±
2.56 V Range, RANGE = 1
Output Noise
See Table I
2 1 024
×
.
REFIN
Gain
Integral Nonlinearity
±
10
ppm of FSR max
Typically 2 ppm
FSR
=
Offset Error
±
3
V typ
AIN(+) = AIN(–) = 2.5 V
Offset Error Drift vs. Temperature
±
10
nV/
°
C typ
Full-Scale Error
±
10
V typ
V
DD
= 3 V
Gain Drift vs. Temperature
±
0.5
ppm/
°
C typ
Power Supply Rejection (PSR)
100
dB typ
Input Range =
±
160 mV, V
IN
= 1/16 V
85
dB typ
Input Range =
±
2.56 V, V
IN
= 1 V
ANALOG INPUTS
Differential Input Voltage Ranges
± 160
mV nom
RANGE = 0
± 2.56
V nom
RANGE = 1
ADC Range Matching
± 2
µV typ
Input Voltage = 159 mV on Both Ranges
Absolute AIN Voltage Limits
GND + 100 mV
V min
V
DD
– 100 mV
V max
Analog Input Current
2
DC Input Current
± 1
nA max
DC Input Current Drift
± 5
pA /°C typ
Normal-Mode Rejection
2, 3
@ 50 Hz
60
dB min
50 Hz ± 1 Hz
@ 60 Hz
94
dB min
60 Hz ± 1 Hz
Common-Mode Rejection
Input Range = ± 160 mV, V
IN
= 1/16 V
@ DC
105
dB min
125 dB typ, 110 dB typ when Input Range = ± 2.56 V
@ 50 Hz
2
100
dB min
50 Hz ± 1 Hz
@ 60 Hz
2
100
dB min
60 Hz ± 1 Hz
REFERENCE INPUT
REFIN Voltage
2.5
V nom
REFIN = REFIN(+) – REFIN(–)
REFIN Voltage Range
2
1
V min
V
DD
V max
Absolute REFIN Voltage Limits
2
GND – 30 mV
V min
V
DD
+ 30 mV
V max
Average Reference Input Current
0.5
A/V typ
Average Reference Input Current Drift
± 0.01
nA/V/°C typ
Normal-Mode Rejection
2, 3
@ 50 Hz
60
dB min
50 Hz
±
1 Hz
@ 60 Hz
94
dB min
60 Hz ± 1 Hz
Common-Mode Rejection
Input Range =
±
160 mV, V
IN
= 1/16 V
@ DC
100
dB typ
@ 50 Hz
110
dB typ
50 Hz ± 1 Hz
@ 60 Hz
110
dB typ
60 Hz
±
1 Hz
LOGIC INPUTS
All Inputs Except SCLK and XTAL1
2
V
INL
, Input Low Voltage
0.8
V max
V
DD
= 5 V
0.4
V max
V
DD
= 3 V
V
INH
, Input High Voltage
2.0
V min
V
DD
= 3 V or 5 V
SCLK Only (Schmitt-Triggered Input)
2
V
T(+)
1.4/2
V min/V max
V
DD
= 5 V
V
T(–)
0.8/1.4
V min/V max
V
DD
= 5 V
V
T(+)
– V
T(–)
0.3/0.85
V min/V max
V
DD
= 5 V
V
T(+)
0.95/2
V min/V max
V
DD
= 3 V
V
T(–)
0.4/1.1
V min/V max
V
DD
= 3 V
V
T(+)
– V
T(–)
0.3/0.85
V min/V max
V
DD
= 3 V
–2–
REV. 0
µ
µ
µ
AD7782
Parameter
AD7782B
Unit
Test Conditions
LOGIC INPUTS (continued)
XTAL1 Only
2
V
INL
, Input Low Voltage
0.8
V max
V
DD
= 5 V
V
INH
, Input High Voltage
3.5
V min
V
DD
= 5 V
V
INL
, Input Low Voltage
0.4
V max
V
DD
= 3 V
V
INH
, Input High Voltage
2.5
V min
V
DD
= 3 V
Input Currents
±
1
µ
A max
V
IN
= V
DD
–70
µ
A max
V
IN
= GND, Typically –40
A at 5 V and –20
A at 3 V
Input Capacitance
10
pF typ
All Digital Inputs
LOGIC OUTPUTS (Excluding XTAL2)
V
OH
, Output High Voltage
2
V
DD
– 0.6
V min
V
DD
= 3 V, I
SOURCE
= 100 µA
V
OL
, Output Low Voltage
2
0.4
V max
V
DD
= 3 V, I
SINK
= 100 µA
V
OH
, Output High Voltage
2
4
V min
V
DD
= 5 V, I
SOURCE
= 200 µA
V
OL
, Output Low Voltage
2
0.4
V max
V
DD
= 5 V, I
SINK
= 1.6 mA
Floating-State Leakage Current
± 10
µA max
Floating-State Output Capacitance
± 10
pF typ
Data Output Coding
Offset Binary
START-UP TIME
From Power-On
300
ms typ
POWER REQUIREMENTS
Power Supply Voltage
V
DD
– GND
2.7/3.6
V min/max
V
DD
= 3 V nom
4.75/5.25
V min/max
V
DD
= 5 V nom
Power Supply Currents
I
DD
Current (Normal Mode)
4
1.5
mA max
V
DD
= 3 V, 1.3 mA typ
1.7
mA max
V
DD
= 5 V, 1.5 mA typ
I
DD
(Power-Down Mode,
CS
= 1)
9
µ
A max
V
DD
= 3 V, 6
µ
A typ
24
µ
A max
V
DD
= 5 V, 20
µ
A typ
C.
2
Guaranteed by design and/or characterization data on production release.
3
When a 28.8 kHz crystal is used, normal mode rejection is improved so that the rejection equals 75 dB at 50
°
C to +85
°
±
1 Hz and equals 66 dB at 60
±
1 Hz.
4
Normal Mode refers to the case where the ADC is running.
Specifications subject to change without notice.
REV. 0
–3–
µ
µ
NOTES
1
Temperature Range –40
AD7782
TIMING CHARACTERISTICS
1, 2
(V
DD
= 2.7 V to 3.6 V or V
DD
= 4.75 V to 5.25 V; GND = 0 V; XTAL = 32.768 kHz; Input Logic 0 = 0 V,
Logic 1 = V
DD
unless otherwise noted.)
Limit at T
MIN
, T
MAX
Parameter
(B Version)
Unit
Conditions/Comments
t
1
30.5176
µs typ
Crystal Oscillator Period
t
ADC
50.54
ms typ
19.79 Hz Update Rate
t
2
0
ns min
CH1
/CH2 Select to
CS
Setup Time
t
3
0
ns min
CS
Falling Edge to DOUT Active
60
ns max
V
DD
= 4.75 V to 5.25 V
80
ns max
V
DD
= 2.7 V to 3.6 V
t
4
2 × t
ADC
ns typ
Channel Settling Time
t
5
3
0
ns min
SCLK Active Edge to Data Valid Delay
4
60
ns max
V
DD
= 4.75 V to 5.25 V
80
ns max
V
DD
= 2.7 V to 3.6 V
t
8
5
10
ns min
Bus Relinquish Time after
CS
Inactive Edge
80
ns max
t
9
0
ns min
CS
Rising Edge to SCLK Inactive Edge Hold Time
t
10
10
ns min
SCLK Inactive to DOUT High
80
ns max
Slave Mode Timing
t
6
100
ns min
SCLK High Pulsewidth
t
7
100
ns min
SCLK Low Pulsewidth
Master Mode Timing
t
6
t
1
/2
µs typ
SCLK High Pulsewidth
t
7
t
1
/2
µs typ
SCLK Low Pulsewidth
t
11
t
1
/2
µs min
DOUT Low to First SCLK Active Edge
4
3t
1
/2
µs max
NOTES
1
Sample tested during initial release to ensure compliance. All input signals are specified with t
R
= t
F
= 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
2
See Figure 2.
3
These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the V
OL
or V
OH
limits.
4
SCLK active edge is falling edge of SCLK.
5
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part
and as such are independent of external bus loading capacitances.
I
SINK
(1.6mA WITH V
DD
= 5V
100
A WITH V
DD
= 3V)
TO OUTPUT
PIN
1.6V
50pF
I
SOURCE
( 200
A WITH V
DD
= 5V
100
A WITH V
DD
= 3V)
Figure 1. Load Circuit for Timing Characterization
–4–
REV. 0
AD7782
CH1/CH2 (I)
t
2
CS (I)
t
3
t
4
t
9
t
8
DOUT/RDY
MSB
LSB
MSB
LSB
t
5
t
10
SLAVE MODE
SCLK (I)
t
7
t
6
t
5
t
11
MASTER MODE
SCLK (O)
t
7
t
6
I = INPUT TO AD7782, O = OUTPUT FROM AD7782
SLAVE MODE IS SELECTED BY TYING THE MODE PIN LOW, WHILE MASTER MODE IS SELECTED BY TYING THE MODE PIN HIGH.
Figure 2. Slave/Master Mode Timing Diagram
C unless otherwise noted)
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Analog Input Voltage to GND . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Reference Input Voltage to GND . . . . . –0.3 V to V
DD
+ 0.3 V
Total AIN/REFIN Current (Indefinite) . . . . . . . . . . . . . 30 mA
Digital Input Voltage to GND . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Digital Output Voltage to GND . . . . . . –0.3 V to V
DD
+ 0.3 V
Operating Temperature Range . . . . . . . . . . . . –40
°
TSSOP Package
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . .97.9
°
C/W
θ
JC
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 14
°
C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215
°
C
C
*
Stresses above those listed under Absolute Maximum Ratings may cause per-
manent damage to the device. This is a stress rating only; functional operation of
the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
°
°
C to +85
°
C
Storage Temperature Range . . . . . . . . . . . . . –65
°
C to +150
°
C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150
°
C
ORDERING GUIDE
Model
Temperature Range Package Description
Package Option
AD7782BRU
–40
°
C to +85
°
C
TSSOP
RU-16
EVAL-AD7782EB
Evaluation Board
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7782 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–5–
ABSOLUTE MAXIMUM RATINGS
*
(T
A
= 25
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