AD8304 prf

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a
160dB-range (100pA-10mA)
Logarithmic Converter
Preliminary Technical Data
AD8304
FEATURES
Optimized for Fiber-Optic Photodiode Interfacing
Eight Full Decades of Range
Law Conformance 0.1 dB from 1 nA to 1 mA
Single Supply Operation (3.6V – 5.5 V)
Complete and Temperature-Stable
Accurate Laser-Trimmed Scaling:
Logarithmic Slope of 10 mV/dB (at VLOG pin)
Basic Logarithmic Intercept at 100 pA
Easy Adjustment of Slope and Intercept
Output Bandwidth of 10 MHz, 15 V/
FUNCTIONAL BLOCK DIAGRAM
10
VPS2
2
PWDN
VPS1
12
PDB
BIAS
VREF
7
VREF
VPDB
6
~10k
Ω
0.5 V
8
VLOG
VSUM
3
5k
Ω
9
BFIN
s Slew-Rate
1,2, or 3-Pole Low Pass Filtering at Output
Miniature 14-Pin Package (TSSOP)
Low Power:
~4 mA Quiescent Current (Enabled)
I
PD
INPT
4
BFNG
13
5
VSUM
APPLICATIONS
High-Accuracy Optical Power Measurement
Wide-Range Baseband Log-Compression
Versatile Detector for APC Loops
1
VNEG
ACOM
14
VOUT
11
PRODUCT DESCRIPTION
The AD8304 is a monolithic logarithmic detector optimized for
the measurement of low-frequency signal power in fiber-optic
supervisory systems. It uses an advanced translinear technique to
provide an exceptionally large dynamic range in a versatile and
easily-used form. Its wide measurement range and accuracy are
achieved using proprietary design techniques and precise laser
trimming. In most applications only a single positive supply
V
P
of
5 V will be required, but 3.6 V to 5.5 V can be used, and certain
applications benefit from the added use of a negative supply,
V
N
.
When using low supply voltages, the log slope is readily altered
to fit the available span. The low quiescent current and chip
disable feature facilitates use in battery-operated applications.
, allowing the slope to be
lowered by shunting it with an external resistance; the addition
of a capacitor at this pin provides a simple low-pass filter. The
intermediate voltage
V
LOG
is buffered in an output stage which
can swing to within about 100 mV of ground (or
V
N
) and the
positive supply,
V
P
, and provides a peak current capacity of
Ω
25
mA. The slope
can be increased using the buffer and a pair of
external feedback resistors. An accurate voltage reference of 2V
is also provided to facilitate the repositioning of the intercept.
±
The input current
I
PD
flows in the collector of an optimally-
scaled NPN transistor, connected in a feedback path around a
low-offset J-FET amplifier. The current-summing input node
operates at a constant voltage, independent of current, with a
default value of 0.5V; this may be adjusted over a wide range,
including ground or below, using an optional negative supply. An
adaptive biasing scheme is provided for reducing the dark current
at very low light input levels. The voltage at pin
VPDB
applies
approximately 0.1 V across the diode for
I
PD
= 100 pA, rising
linearly with current to 2.6V of net bias at
I
PD
= 10 mA. The input
pin
INPT
is flanked by the guard pins
VSUM
which track the
voltage at the summing node to minimize leakage.
Many operational modes are possible. For example, low pass
filters of up to three poles may be implemented, to reduce the
output noise at low input currents. The buffer may also serve as
a precise comparator, with or without hysteresis, using the 2 V
reference, for example, in alarm applications. The incremental
bandwidth of a translinear logarithmic amplifier is inherently
lower as the current level diminishes. At the 1 nA level, the
AD8304’s bandwidth is about 2 kHz, but this increases in
proportion to
I
PD
up to a maximum value of 10 MHz.
The AD8304 is available in a 14-pin TSSOP package and
specified for operation from -40
°
C to +85
°
C.
REV. PrF 10/3/01
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its use;
nor for any infringements of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise under
any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 ©Analog Devices, Inc., 2001
µ
The default value of the logarithmic slope at the output
VLOG
is
accurately scaled to 10 mV/dB (200 mV/ decade). The
resistance at this output is exactly 5 k
AD8304
AD8304-SPECIFICATIONS
V
P
= 5V,
V
N
= 0,
T
A
= 25
°
C, unless otherwise noted
Parameters
Conditions
Min
Typ
Max Units
INPUT INTERFACE
Pin 4,
INPT
Specified Current Range
Flows toward
INPT
pin
200p
10m
A
Input Current Limits
100p
20m
A
Input Node Voltage
Internally pre-set; may be altered
−
0.5
V
40
°
C < T
A
< +85
°
C, 3.6V <
V
P
<5.5V
PHOTODIODE BIAS
1
Established between pin 6,
VPDB,
and pin 4
Minimum Value
I
PD
= 300 pA
0.1
V
Maximum Value
I
PD
= 10 mA
2.6
V
LOGARITHMIC OUTPUT
Pin 8,
VLOG
Logarithmic Slope
Laser-trimmed at 25
°
C
9.75
10
10.25
mV/dB
0°
C < T
A
< +70
°
C, 3.6V <
V
P
<5.5V
9.7
10
10.3
mV/dB
Logarithmic Intercept
Laser-trimmed at 25
°
C
50
100
150
pA
0°
C < T
A
< +70
°
C, 3.6V <
V
P
<5.5V
25
100
175
pA
Logarithmic Law Conformance
1 nA <
I
PD
< 1 mA
0.1
dB
0°
C < T
A
< +70
°
C, 3.6V <
V
P
<5.5V
1.6
dB
Voltage Swing
0
1.6
V
Output Resistance
Laser-trimmed at 25
°
C
4.95
5
5.05
k
Ω
REFERENCE OUTPUT
Pin 7,
VREF
Voltage wrt Ground
Laser-trimmed at 25
°
C
1.96
2
2.04
V
−
40
°
C <
T
A
< +85
°
C, 3.6V <
V
P
<5.5V
2
V
Maximum Output Current
Sourcing (grounded load)
10
20
mA
OUTPUT BUFFER
Pin 9,
BFIN
; pin 13,
BFNG
; pin 11,
VOUT
Input Offset Voltage
2
10
mV
Input Bias Current
Flowing out of pins 9 or 13
0.4
µ
A
Output Range
R
L
= 5 k
Ω
to ground
4.9
V
General Upper Limit
R
L
= 1 k
Ω
to ground
V
P
-0.15
V
Peak Source/Sink Current
25
mA
Small Signal Bandwidth
2
I
PD
> 1
µ
A (see Performance Curves)
16
MHz
Slew Rate
0.2V to 4.8V output swing
15
V/
µ
s
POWER DOWN INPUT
Pin 2,
PWDN
Logic Level, HI State
−
40
°
C <
T
A
< +85
°
C, 3.6V <
V
P
<5.5V
V
P
- 0.5
V
Logic Level, LO State
−
40
°
C <
T
A
< +85
°
C, 3.6V <
V
P
<5.5V
0.5
V
POWER SUPPLY
Pins 10 & 12,
VPS1
&
VPS2
; pin 1,
VNEG
Positive Supply Voltage
3.6
5
5.5
V
Quiescent Current
−
40
°
C <
T
A
< +85
°
C, 3.6V <
V
P
<5.5V
4
5.3
mA
Negative Supply Voltage
(Optional)
(
V
P
−
V
N
)
≤
8 V
0
-3
V
Notes
1) This bias is internally arranged to track the input voltage at
INPT
; it is not specified relative to ground
2) Output Noise and Incremental Bandwidth are functions of Input Current: see performance curves
REV. PrF 10/3/2001
- 2 -
AD8304
V
N
…...…………….……………...8 V
Input Current ………………………………………...20mA
Internal Power Dissipation …. …………….….……..TBD
θ
JA
……………………………………..…...…...150
Pin Function Desc
riptions
Pin
Name
Function
1
VNEG
Optional Negative Supply,
V
N
(this
pin is usually grounded; for details of
usage see APPLICATIONS)
C/W
Maximum Junction Temperature …...…….……..+125
°
°
C
2
PWDN
Power Down Control Input. Device
is active when PWDN is taken LOW
Operating Temperature Range .…….…..-40
°
C to +85
°
C
3,5
VSUM
Guard Pins. Used to shield the INPT
current line.
Storage Temperature Range …………..-65
°
C to +150
°
C
Lead Temperature Range (Soldering 60 sec) …… +300
°
C
4
INPT
Photodiode Current Input. Usually
connected to photodiode anode such
that photo-current flows into INPT.
*Stresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional
operation of the device at these or any other conditions above those indicated
in the operational section of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device
reliability.
6
VPDB
Photodiode Biaser Output. May be
connected to photodiode cathode to
provide adaptive bias control
7
VREF
Voltage Reference output of 2.0 V
8
VLOG
Output of the logarithmic front-end
9
BFIN
Buffer Amplifier non-inverting input.
10
VPS2
Positive Supply,
V
P
(3.6 V to 5.5 V)
11
VOUT
Buffer Output
12
VPS1
Positive Supply,
V
P
(3.6 V to 5.5 V)
13
BFNG
Buffer Amplifier inverting input.
14
ACOM
Analog Ground
CAUTION
ESD
(electrostatic
discharge)
sensitive
device.
Ele c tro s ta tic
c ha rg es
as
hig h
as
4 00 0
V
re ad ily
accum
ulate
on
the
hum
an
body
and
test
equipm e nt
a nd
c an
d is c ha r g e
with ou t
de tec tio n.
Altho ug h
the
AD830 4
features
proprietary
ESD
protection
c irc uitry,
p e rm a ne n t
d a m a g e
m a y
o c cu r
o n
devices
subjected
to
high
energ
y
[>250
V
HBM]
elec tro static
d is c ha rg e s .
T herefo re ,
p ro pe r
E S D
precautions
are
recom
m
ended
to
avoid
perform an c e
d e g ra d a tio n
or
lo s s
of
fu nc tion ality.
W
A
ESD
SENSITIVE
DEVICE
ORDERING GUIDE
Model
Temp. Range
Package Description
Package Option
AD8304ARU
AD8304ARU-REEL7
AD8304-EVAL
-40
°
C to +85
°
C
Tube, 14-Lead TSSOP
7" Tape and Reel
Evaluation Board
RU-14
PIN CONFIGURATION
VNEG
1
14
ACOM
PWDN
2
13
BFNG
AD8304
TOP VIEW
(Not To Scale)
VSUM
3
12
VPS1
INPT
4
11
VOUT
VSUM
5
10
VPS2
VPDB
6
9
BFIN
VREF
7
8
VLOG
14L-TSSOP
REV. PrF 10/3/2001
- 3 -
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage
V
P
−
N
G
AD8304
Typical DC Performance Characteristics
(
V
P
= 5V,
V
N
= -0.5V,
T
A
= 25
°
C, unless otherwise noted)
0.5005
1.8
0.5
1.6
1.4
0.4995
1.2
0.499
1
0.4985
0.8
0.498
0.6
0.4
0.4975
0.2
0.497
0.00E+00
1.00E-03
2.00E-03
3.00E-03
4.00E-03
5.00E-03
6.00E-03
7.00E-03
0
Ipd - Amps
1.00E-10
1.00E-09
1.00E-08
1.00E-07
1.00E-06
1.00E-05
1.00E-04
1.00E-03
1.00E-02
Input Current - Amps
TPC 1. V
LOG
vs. I
PD
TPC 4.
Variation of
V
SUM
vs
.
I
PD
2
1
0.8
1.5
0.6
0.4
0.2
1
0
V
PDB
-0.2
-0.4
0.5
-0.6
V
INPT
-0.8
0
-1
1.00E-10
1.00E-09
1.00E-08
1.00E-07
1.00E-06
1.00E-05
1.00E-04
1.00E-03
1.00E-02
1.00E-10
1.00E-09
1.00E-08
1.00E-07
1.00E-06
1.00E-05
1.00E-04
1.00E-03
1.00E-02
Ipd - Amps
Input Current - Amps
TPC 2.
Logarithmic Conformance
TPC 5. V
PDB
vs
.
I
PD
4.5
10
100 nA
10 uA
10 nA
1 uA
4
100 uA
0
3.5
10 mA
1 mA
-10
1 nA
3
-20
2.5
-30
2
-40
1.5
-50
1
-60
0.5
0
-70
0.0E+00
1.0E-06
2.0E-06
3.0E-06
4.0E-06
5.0E-06
6.0E-06
7.0E-06
8.0E-06
9.0E-06
1.0E-05
1.00E+02
1.00E+03
1.00E+04
1.00E+05
1.00E+06
1.00E+07
1.00E+08
Frequency - Hz
Time (seconds)
TPC 3.
Log Amplifier Small Signal Frequency Response
TPC 6.
Unity Gain Buffer Stability when Driving Capacitive
Loads Up to 350 pF
REV. PrF 10/3/2001
- 4 -
 AD8304
Typical DC Performance Characteristics
(
V
P
= 5V,
V
N
= -0.5V,
T
A
= 25
°
C, unless otherwise noted)
TPC 7.
Log Conformance Distribution at 25
°
C
TPC 10.
Slope Drift
vs
. Temperature, 3 Sigma to Either Side of
Mean
TPC 8.
Log Conformance Distribution at 0
°
C
TPC 11.
Intercept Drift
vs
. Temperature, 3 Sigma to Either Side
of Mean
TPC 9.
Log Conformance Distribution at 70
°
C
REV. PrF 10/3/2001
- 5 -
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