AD9806 0

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a
Complete 10-Bit 18 MSPS
CCD Signal Processor
AD9806
FEATURES
Pin-Compatible with Industry Standard AD9803
18 MSPS Correlated Double Sampler (CDS)
Low Noise PGA with 0 dB to 34 dB Gain Range
Low Noise Clamp Circuits
Analog Preblanking Function
10-Bit 18 MSPS A/D Converter
AUX Input with Input Clamp and PGA
Direct ADC Input with Input Clamp
AUXMID Input with PGA
3-Wire Serial Interface for Digital Control
Two Auxiliary 8-Bit DACs
3 V Single Supply Operation
Low Power: 65 mW @ 2.7 V Supply
48-Lead LQFP Package
PRODUCT DESCRIPTION
The AD9806 is a complete analog signal processor for CCD
applications. It features an 18 MHz single-channel architecture
designed to sample and condition the outputs of interlaced and
progressive scan area CCD arrays. The AD9806’s signal chain
consists of an input clamp, correlated double sampler (CDS),
digitally programmable gain amplifier (PGA), black level clamp,
and 10-bit A/D converter. Additional input modes are provided
for processing analog video signals.
The internal registers are programmed through a 3-wire serial
digital interface. Programmable features include gain adjust-
ment, black level adjustment, input configuration, and power-
down modes.
The AD9806 operates from a single 3 V power supply, typically
dissipating 75 mW. Packaged in a space-saving 48-lead LQFP,
the AD9806 is specified over an operating temperature range of
–20°C to +85 C.
APPLICATIONS
Camcorders (8 mm and DVC)
Digital Still Cameras
FUNCTIONAL BLOCK DIAGRAM
PBLK
CLPOB
0dB
~
34dB
CLAMP
AD9806
CCDIN
CDS
PGA
10
MUX
S/H
ADC
DOUT
CLAMP
CLPDM
0dB
~
15dB
–4
~
14dB
PGA
PGA
REF
VRT
VRB
8-BIT
DAC
10-BIT
DAC
DAC1
CLAMP
DAC2
8
-BIT
DAC
INTF
TIMING
GENERATOR
3
3-W INTF ADCIN AUXIN
AUXMID
SHP SHD ADCCLK
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
AD9806–SPECIFICATIONS
GENERAL SPECIFICATIONS
Parameter
(T
MIN
to T
MAX
, AVDD = DVDD = 3.0 V, f
ADCCLK
= 18 MHz, unless otherwise noted.)
Min
Typ
Max
Unit
TEMPERATURE RANGE
Operating
–20
+85
°
C
Storage
–65
+150
°
C
POWER SUPPLY VOLTAGE
(For Functional Operation)
2.7
3.6
V
Analog, Digital, Digital Driver
POWER CONSUMPTION
(Selected through Serial Interface D-Reg)
Normal Operation (D-Reg 00)
(Specified Under Each Mode of Operation)
High-Speed AUX Mode (D-Reg 01)
(Specified Under AUX-Mode)
Reference Standby (D-Reg 10)
5
mW
Total Shut-Down Mode (D-Reg 11)
1
mW
MAXIMUM CLOCK RATE
(Specified Under Each Mode of Operation)
MHz
A/D CONVERTER
Resolution
10
Bits
Differential Nonlinearity (DNL)
±0.5
±1.0
LSB
No Missing Codes
GUARANTEED
Full-Scale Input Voltage
1.0
V
VOLTAGE REFERENCE
Reference Top Voltage (VRT)
2.0
V
Reference Bottom Voltage (VRB)
1.0
V
Specifications subject to change without notice.
DIGITAL SPECIFICATIONS
Parameter
(DRVDD = 2.7 V, C
L
= 20 pF.)
Symbol
Min
Typ
Max
Unit
LOGIC INPUTS
High Level Input Voltage
V
IH
2.1
V
Low Level Input Voltage
V
IL
0.6
V
High Level Input Current
I
IH
10
A
Low Level Input Current
I
IL
10
A
Input Capacitance
C
IN
10
pF
LOGIC OUTPUTS
High Level Output Voltage (I
OH
= 2 mA)
V
OH
2.2
V
Low Level Output Voltage (I
OL
= 2 mA)
V
OL
0.5
V
SERIAL INTERFACE TIMING (Figure 7)
Maximum SCLK Frequency
10
MHz
SDATA to SCLK Setup
t
DS
10
ns
SCLK to SDATA Hold
t
DH
10
ns
SLOAD to SCLK Setup
t
LS
10
ns
SCLK to SLOAD Hold
t
LH
10
ns
Specifications subject to change without notice.
–2–
REV. 0
µ
µ
AD9806
CCD-MODE SPECIFICATIONS
Parameter
(T
MIN
to T
MAX
, AVDD = DVDD = 3.0 V, f
ADCCLK
= f
SHP
= f
SHD
= 18 MHz, unless otherwise noted.)
Min
Typ
Max
Unit
POWER CONSUMPTION
V
DD
= 2.7
65
mW
V
DD
= 3.0
75
mW
V
DD
= 3.3
85
mW
MAXIMUM CLOCK RATE
18
MHz
CDS
Gain
0
dB
Allowable CCD Reset Transient
1
500
mV
Max Input Range before Saturation
1
1000
mV p-p
PGA
Gain Control Resolution
10
Bits
Gain Range (See Figure 5a for Gain Curve)
Low Gain (Code 95)
2
–1
0
+1
dB
Max Gain (1023)
2
32
33
34
dB
BLACK LEVEL CLAMP
Clamp Level (Selected through Serial Interface E-Reg)
CLP0 (E-Reg 00)
32
LSB
CLP1 (E-Reg 01)
48
LSB
CLP2 (E-Reg 10)
64
LSB
CLP3 (E-Reg 11)
16
LSB
SIGNAL-TO-NOISE RATIO
3
(@ Low PGA Gain)
74
dB
TIMING SPECIFICATIONS
4
Pipeline Delay
9
Cycles
Internal Clock Delay
5
(t
ID
)
3
ns
Inhibited Clock Period (t
INHIBIT
)
10
ns
Output Delay (t
OD
)
14.5
16
ns
Output Hold Time (t
HOLD
)
6
ns
ADCCLK, SHP, SHD Clock Period
47
55.6
ns
ADCCLK High-Level/Low-Level
20
28
ns
SHP, SHD Minimum Pulsewidth
10
14
ns
SHP Rising Edge to SHD Rising Edge
20
28
ns
NOTES
1
Input signal characteristics defined as follows:
500mV TYP
RESET
TRANSIENT
1V MAX
INPUT
SIGNAL RANGE
200mV MAX
OPTICAL
BLACK PIXEL
2
Use equations on page 8 to calculate gain.
3
SNR = 20 log
10
(Full-Scale Voltage/RMS Output Noise).
4
20 pF loading; timing shown in Figure 1.
5
Internal aperture delay for actual sampling edge.
Specifications subject to change without notice.
REV. 0
–3–
AD9806–SPECIFICATIONS
AUX-MODE SPECIFICATIONS
Parameter
(T
MIN
to T
MAX
, AVDD = DVDD = 3.0 V, f
ADCCLK
= 18 MHz, unless otherwise noted.)
Min
Typ
Max
Unit
POWER CONSUMPTION
Normal (D-Reg 00)
50
mW
High-Speed (D-Reg 01)
95
mW
MAXIMUM CLOCK RATE
Normal (D-Reg 00)
18
MHz
High-Speed (D-Reg 01)
28.6
MHz
PGA (Gain Selected through Serial Interface F-Reg)
Max Input Range
700
mV p-p
Max Output Range
1000
mV p-p
Gain Control Resolution
7
Bits
Gain Range
Min Gain (Code 128)
–2
dB
Max Gain (Code 255)
15
dB
ACTIVE CLAMP
Clamp Level (Selected through Serial Interface E-Reg)
CLP0 (E-Reg 00)
32
LSB
CLP1 (E-Reg 01)
48
LSB
CLP2 (E-Reg 10)
64
LSB
CLP3 (E-Reg 11)
16
LSB
TIMING SPECIFICATIONS
1
Pipeline Delay
9
Cycles
Internal Clock Delay (t
ID
)
Output Delay (t
OD
)
14.5
16
ns
Output Hold Time (t
HOLD
)
7
ns
NOTES
1
20 pF loading; timing shown in Figure 2.
Specifications subject to change without notice.
AUXMID-MODE SPECIFICATIONS
Parameter
(T
MIN
to T
MAX
, AVDD = DVDD = 3.0 V, f
ADCCLK
= 18 MHz, unless otherwise noted.)
Min
Typ
Max
Unit
POWER CONSUMPTION
50
mW
MAXIMUM CLOCK RATE
18
MHz
PGA (Gain Selected through Serial Interface F-Reg)
Max Input Range
700
mV p-p
Max Output Range
1000
mV p-p
Gain Control Resolution
9
Bits
Gain Range (See Figure 5b for Gain Curve)
Min Gain (Code 512)
–4
dB
Max Gain (Code 1023)
14
dB
MIDSCALE OFFSET LEVEL (AT MAX PGA GAIN)
462
512
562
LSB
TIMING SPECIFICATIONS
1
Pipeline Delay
9
Cycles
Internal Clock Delay (t
ID
)
Output Delay (t
OD
)
14.5
16
ns
Output Hold Time (t
HOLD
)
7
ns
NOTES
1
20 pF loading; timing shown in Figure 2.
Specifications subject to change without notice.
–4–
REV. 0
ADC-MODE SPECIFICATIONS
Parameter
AD9806
(T
MIN
to T
MAX
, AVDD = DVDD = 3.0 V, f
ADCCLK
= 18 MHz, unless otherwise noted.)
Min
Typ
Max
Unit
POWER CONSUMPTION
(Same as AUX-MODE)
MAXIMUM CLOCK RATE
(Same as AUX-MODE)
ACTIVE CLAMP
(Same as AUX-MODE)
TIMING SPECIFICATIONS
1
(Same as AUX-MODE)
Specifications subject to change without notice.
DAC SPECIFICATIONS (DAC1 and DAC2)
Parameter
Min
Typ
Max
Unit
RESOLUTION
8
Bits
MIN OUTPUT
0.1
V
MAX OUTPUT
VDD – 0.1
V
MAX CURRENT LOAD
1
mA
MAX CAPACITIVE LOAD
500
pF
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS
Parameter
With Respect To
Min
Max
Unit
AVDD1, AVDD2
AVSS
–0.3
+3.9
V
DVDD1, DVDD2
DVSS
–0.3
+3.9
V
DRVDD
DRVSS
–0.3
+3.9
V
Digital Outputs
DRVSS
–0.3
DRVDD + 0.3
V
SHP, SHD, DATACLK
DVSS
–0.3
DVDD + 0.3
V
CLPOB, CLPDM, PBLK
DVSS
–0.3
DVDD + 0.3
V
SCK, SL, SDATA
DVSS
–0.3
DVDD + 0.3
V
VRT, VRB, CMLEVEL
AVSS
–0.3
AVDD + 0.3
V
CCDIN, CLPOUT, CLPREF, CLPBYP
AVSS
–0.3
AVDD + 0.3
V
Junction Temperature
150
°C
Lead Temperature (10 sec)
300
°C
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
AD9806KST
–20°C to +85°C
Thin Plastic Quad Flatpack (LQFP)
ST-48
THERMAL CHARACTERISTICS
Thermal Resistance
48-Lead LQFP Package
θ
JA
= 92
°
C
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9806 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–5–
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