AD9852 b

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a
CMOS 300 MSPS
Complete-DDS
AD9852
FEATURES
300 MHz Internal Clock Rate
FSK, BPSK, PSK, CHIRP, AM Operation
Dual Integrated 12-Bit D/A Converters
Ultrahigh-Speed Comparator, 3 ps RMS Jitter
Excellent Dynamic Performance: 80 dB SFDR @ 100 MHz
(
3.3 V Single Supply
Multiple Power-Down Functions
Single-Ended or Differential Input Reference Clock
Small 80-Lead LQFP Packaging
1 MHz) A
OUT
4
to 20
Programmable Reference Clock Multiplier
Dual 48-Bit Programmable Frequency Registers
Dual 14-Bit Programmable Phase Offset Registers
12-Bit Amplitude Modulation and Programmable
Shaped On/Off Keying Function
Single Pin FSK and BPSK Data Interface
PSK Capability Via I/O Interface
Linear or Nonlinear FM Chirp Functions with Single
Pin Frequency “Hold” Function
Frequency-Ramped FSK
<25 ps RMS Total Jitter in Clock Generator Mode
Automatic Bidirectional Frequency Sweeping
SIN(x)/x Correction
Simplified Control Interface
10 MHz Serial, 2-Wire or 3-Wire SPI-Compatible, or
100 MHz Parallel 8-Bit Programming
APPLICATIONS
Agile, L.O. Frequency Synthesis
Programmable Clock Generator
FM Chirp Source for Radar and Scanning Systems
Test and Measurement Equipment
Commercial and Amateur RF Exciter
GENERAL DESCRIPTION
The AD9852 digital synthesizer is a highly integrated device
that uses advanced DDS technology, coupled with an internal
high-speed, high-performance D/A converter to form a digitally
programmable agile synthesizer function. When referenced to
an accurate clock source, the AD9852 generates a highly stable,
frequency-phase-amplitude-programmable cosine output that
can be used as an agile L.O. in communications, radar, and many
other applications. The AD9852’s innovative high-speed DDS
core provides 48-bit frequency resolution (1 microHertz tuning
resolution with 300 MHz SYSCLK). Maintaining 17 bits assures
excellent SFDR. The AD9852’s circuit architecture allows the
generation of output signals at frequencies up to 150 MHz,
(
continued on page 15)
FUNCTIONAL BLOCK DIAGRAM
SYSTEM CLOCK
DDS CORE
DIGITAL MULTIPLIERS
REF CLK
MULTI-
PLIER
–20
INV.
SINC
FILTER
REFERENCE
CLOCK IN
REF
CLK
BUFFER
I
12-BIT
COSINE DAC
ANALOG
OUT
12
12
48
48
17
17
SYSTEM
CLOCK
DIFF/SINGLE
SELECT
MUX
DAC R
SET
SYSTEM
CLOCK
48
14
Q
12-BIT
CONTROL
DAC
ANALOG
OUT
12
D
M
X
FSK/BPSK/HOLD
DATA IN
3
MUX
MUX
MUX
DELTA
FREQUENCY
RATE TIMER
SYSTEM
CLOCK
PROGRAMMABLE
AMPLITUDE AND
RATE CONTROL
ANALOG
IN
2
SYSTEM
CLOCK
COMPARATOR
48
48
48
14
14
12
CLOCK
OUT
DELTA
FREQUENCY
WORD
FREQUENCY
TUNING
WORD 1
FREQUENCY
TUNING
WORD 2
1ST 14-BIT PHASE/
OFFSET WORD
2ND 14-BIT PHASE/
OFFSET WORD
AM MODULATION 12-BIT DC
CONTROL
MODE SELECT
PROGRAMMING REGISTERS
SHAPED
ON/OFF
KEYING
SYSTEM
CLOCK
SYSTEM
CLOCK
AD9852
CK
Q
2
BUS
D
BIDIRECTIONAL
INTERNAL/EXTERNAL
I/O UPDATE
CLOCK
GND
INT
INTERNAL
PROGRAMMABLE
UPDATE CLOCK
I/O PORT BUFFERS
EXT
+V
S
READ WRITE SERIAL/
PARALLEL
SELECT
6-BIT ADDRESS
OR SERIAL
PROGRAMMING
LINES
8-BIT
PARALLEL
LOAD
MASTER
RESET
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
4
 AD9852
TABLE OF CONTENTS
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1
FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . 1
TABLE OF CONTENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Test Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 5
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Single-Tone (Mode 000) . . . . . . . . . . . . . . . . . . . . . . . . . 15
Unramped FSK (Mode 001) . . . . . . . . . . . . . . . . . . . . . . 15
Ramped FSK (Mode 010) . . . . . . . . . . . . . . . . . . . . . . . . 16
Chirp (Mode 011) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Basic FM Chirp Programming Steps . . . . . . . . . . . . . . . . 19
BPSK (Mode 100) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Internal and External Update Clock . . . . . . . . . . . . . . . . . 21
Shaped On/Off Keying . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Cosine DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Control DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Inverse SINC Function . . . . . . . . . . . . . . . . . . . . . . . . . . 23
REFCLK Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Parallel I/O Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
GENERAL OPERATION OF THE
Instruction Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Notes on Serial Port Operation . . . . . . . . . . . . . . . . . . . . 28
MSB/LSB TRANSFERS . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
POWER DISSIPATION AND
THERMAL CONSIDERATIONS . . . . . . . . . . . . . . . . . 29
EVALUATION OF OPERATING CONDITIONS . . . . . . 31
THERMALLY ENHANCED PACKAGE
EVALUATION BOARD INSTRUCTIONS . . . . . . . . . . . 33
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
GENERAL OPERATING INSTRUCTIONS . . . . . . . . . . 33
Clock Input, J25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Three-State Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Low-Pass Filter Testing . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Observing the Unfiltered IOUT1 and the
Unfiltered IOUT2 DAC Signals . . . . . . . . . . . . . . . . . . 34
Observing the Filtered IOUT1 and the
Filtered IOUT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Observing the Filtered IOUT1 and the
Filtered IOUT1B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
To Connect High-Speed Comparator . . . . . . . . . . . . . . . 34
Single-Ended Configuration . . . . . . . . . . . . . . . . . . . . . . . 34
–2–
REV. B
AD9852
(V
S
= 3.3 V
5%, R
SET
= 3.9 k
external reference clock frequency = 30 MHz with REFCLK
Multiplier enabled at 10
for AD9852ASQ, external reference clock frequency = 20 MHz with REFCLK Multiplier enabled at 10
for AD9852AST unless otherwise noted.)
Test
AD9852ASQ
AD9852AST
Parameter
Temp Level Min
Typ
Max
Min
Typ
Max
Unit
REF CLOCK INPUT CHARACTERISTICS
1
Internal System Clock Frequency Range
REFCLK Multiplier Enabled
Full
VI
20
300
20
200
MHz
REFCLK Multiplier Disabled
Full
VI
DC
300
DC
200
MHz
External REF Clock Frequency Range
REFCLK Multiplier Enabled
Full
VI
5
75
5
50
MHz
REFCLK Multiplier Disabled
Full
VI
DC
300
DC
200
MHz
Duty Cycle
25°CIV
45
50
55
45
50
55
%
Input Capacitance
25°CIV
3
3
F
Input Impedance
25°C IV
100
100
kΩ
Differential Mode Common-Mode Voltage Range
Minimum Signal Amplitude
2
25°C IV
800
800
mV p-p
Common-Mode Range
25°C IV
1.6
1.75
1.9
1.6
1.75
1.9
V
V
IH
(Single-Ended Mode)
25°C IV
2.3
2.3
V
V
IL
(Single-Ended Mode)
25°CIV
1
1
V
DAC STATIC OUTPUT CHARACTERISTICS
Output Update Speed
Full
I
300
200
MSPS
Resolution
25°C IV
12
12
Bits
Cosine and Control DAC’s Full-Scale
Output Current
25°C IV
5
10
20
5
10
20
mA
Gain Error
25°C I
–6
+2.25 –6
+2.25
% FS
Output Offset
25°CI
2
2
µA
Differential Nonlinearity
25°C I
0.3
1.25
0.3
1.25
LSB
Integral Nonlinearity
25°C I
0.6
1.66
0.6
1.66
LSB
Output Impedance
25°C IV
100
100
kΩ
Voltage Compliance Range
25°C I
–0.5
+1.0
–0.5
+1.0
V
DAC DYNAMIC OUTPUT CHARACTERISTICS
DAC Wideband SFDR
1 MHz to 20 MHz A
OUT
25°C V
58
58
dBc
20 MHz to 40 MHz A
OUT
25°C V
56
56
dBc
40 MHz to 60 MHz A
OUT
25°C V
52
52
dBc
60 MHz to 80 MHz A
OUT
25°C V
48
48
dBc
80 MHz to 100 MHz A
OUT
25°C V
48
48
dBc
100 MHz to 120 MHz A
OUT
25°C V
48
dBc
DAC Narrowband SFDR
10 MHz A
OUT
(±1 MHz)
25°C V
83
83
dBc
10 MHz A
OUT
(±250 kHz)
25°C V
83
83
dBc
10 MHz A
OUT
(±50 kHz)
25°C V
91
91
dBc
41 MHz A
OUT
(±1 MHz)
25°C V
82
82
dBc
41 MHz A
OUT
(±250 kHz)
25°C V
84
84
dBc
41 MHz A
OUT
(±50 kHz)
25°C V
89
89
dBc
119 MHz A
OUT
(±1 MHz)
25°C V
71
dBc
119 MHz A
OUT
(±250 kHz)
25°C V
77
dBc
119 MHz A
OUT
(±50 kHz)
25°C V
83
dBc
Residual Phase Noise
(A
OUT
= 5 MHz, Ext. CLK = 30 MHz,
REFCLK
Multiplier Engaged at 10×)
1 kHz Offset
25°C V
140
140
dBc/Hz
10 kHz Offset
25°C V
138
138
dBc/Hz
100 kHz Offset
25°C V
142
142
dBc/Hz
(A
OUT
= 5 MHz, Ext. CLK = 300 MHz,
REFCLK Multiplier Bypassed)
1 kHz Offset
25°C V
142
142
dBc/Hz
10 kHz Offset
25°C V
148
148
dBc/Hz
100 kHz Offset
25°C V
152
152
dBc/Hz
REV. B
–3–
SPECIFICATIONS
 AD9852–SPECIFICATIONS
(continued)
Test
AD9852ASQ
AD9852AST
Parameter
Temp Level Min
Typ
Max
Min
Typ
Max
Unit
DAC DYNAMIC OUTPUT CHARACTERISTICS (continued)
Pipeline Delays
3, 4, 5
DDS Core (Phase Accumulator and
Phase-to-Amp Converter)
25°C IV
33
33
SysClk Cycles
Frequency Accumulator
25°C IV
26
26
SysClk Cycles
Inverse Sinc Filter
25°C IV
16
16
SysClk Cycles
Digital Multiplier
25°C IV
9
9
SysClk Cycles
DAC
25°C IV
1
1
SysClk Cycles
I/O Update Clock (INT Mode)
25°C IV
2
2
SysClk Cycles
I/O Update Clock (EXT Mode)
25°C IV
3
3
SysClk Cycles
MASTER RESET DURATION
25°C IV
10
10
SysClk Cycles
COMPARATOR INPUT CHARACTERISTICS
Input Capacitance
25°CV
3
3
F
Input Resistance
25°C IV
500
500
kΩ
Input Current
25°CI
±1
±5
±1
±5
µA
Hysteresis
25°C IV
10
20
10
20
mV p-p
COMPARATOR OUTPUT CHARACTERISTICS
Logic “1” Voltage, High Z Load
Full
VI
3.1
3.1
V
Logic “0” Voltage, High Z Load
Full
VI
0.16
0.16
V
Output Power, 50 Ω Load, 120 MHz Toggle Rate 25°C I
9
11
9
11
dBm
Propagation Delay
25°CIV
3
3
s
Output Duty Cycle Error
6
25°C I
–10
±1
+10
–10
±1
+10
%
Rise/Fall Time, 5 pF Load
25°CV
2
2
s
Toggle Rate, High Z Load
25°C IV
300
350
300
350
MHz
Toggle Rate, 50 Ω Load
25°C IV
375
400
375
400
MHz
Output Cycle-to-Cycle Jitter
7
25°C IV
4.0
4.0
ps rms
COMPARATOR NARROWBAND SFDR
8
10 MHz (±1 MHz)
25°C V
84
84
dBc
10 MHz (±250 kHz)
25°C V
84
84
dBc
10 MHz (±50 kHz)
25°C V
92
92
dBc
41 MHz (±1 MHz)
25°C V
76
76
dBc
41 MHz (±250 kHz)
25°C V
82
82
dBc
41 MHz (±50 kHz)
25°C V
89
89
dBc
119 MHz (±1 MHz)
25°C V
73
dBc
119 MHz (±250 kHz)
25°C V
73
dBc
119 MHz (±50 kHz)
25°C V
83
dBc
CLOCK GENERATOR OUTPUT JITTER
8
5 MHz A
OUT
25°C V
23
23
ps rms
40 MHz A
OUT
25°C V
12
12
ps rms
100 MHz A
OUT
25°C V
7
7
ps rms
PARALLEL I/O TIMING CHARACTERISTICS
T
ASU
(Address Setup Time to
WR
Signal Active) Full
IV
8.0
7.5
8.0
7.5
ns
T
ADHW
(Address Hold Time to
WR
Signal Inactive) Full
IV
0
0
ns
T
DSU
(Data Setup Time to
WR
Signal Inactive) Full
IV
3.0
1.6
3.0
1.6
ns
T
DHD
(Data Hold Time to
WR
Signal Inactive) Full
IV
0
0
ns
T
WRLOW
(
WR
Signal Minimum Low Time)
Full
IV
2.5
1.8
2.5
1.8
ns
T
WRHIGH
(
WR
Signal Minimum High Time)
Full
IV
7
7
ns
T
WR
(Minimum WRITE Time)
Full
IV
10.5
10.5
ns
T
ADV
(Address to Data Valid Time)
Full
V
15
15
15
15
ns
T
ADHR
(Address Hold Time to
RD
Signal Inactive) Full
IV
5
5
ns
T
RDLOV
(
RD
Low-to-Output Valid)
Full
IV
15
15
ns
T
RDHOZ
(
RD
High-to-Data Three-State)
Full
IV
10
10
ns
SERIAL I/O TIMING CHARACTERISTICS
T
PRE
(
CS
Setup Time)
Full
IV
30
30
ns
T
SCLK
(Period of Serial Data Clock)
Full
IV
100
100
ns
T
DSU
(Serial Data Setup Time)
Full
IV
30
30
ns
T
SCLKPWH
(Serial Data Clock Pulsewidth High) Full
IV
40
40
ns
T
SCLKPWL
(Serial Data Clock Pulsewidth Low) Full
IV
40
40
ns
T
DHLD
(Serial Data Hold Time)
Full
IV
0
0
ns
T
DV
(Data Valid Time)
Full
V
30
30
ns
–4–
REV. B
AD9852
Test
AD9852ASQ
AD9852AST
Parameter
Temp Level Min
Typ
Max
Min
Typ
Max
Unit
SERIAL I/O TIMING CHARACTERISTICS (continued)
CMOS LOGIC INPUTS
9
Logic “1” Voltage
25°CI
.2
.2
V
Logic “0” Voltage
25°CI
.8
.8 V
Logic “1” Current
25°CIV
±5
±12
µA
Logic “0” Current
25°CIV
±5
±12
µA
Input Capacitance
25°CV
3
3
F
POWER SUPPLY
10
+V
S
Current
11
25°C I
815
922
585
660
mA
+V
S
Current
12
25°C I
640
725
465
520
mA
+V
S
Current
13
25°C I
585
660
425
475
mA
P
DISS
11
25°C I
2.70
3.20
1.93
2.39
W
P
DISS
12
25°C I
2.12
2.52
1.53
1.81
W
P
DISS
13
25°C I
1.93
2.29
1.40
1.65
W
P
DISS
Power-Down Mode
25°CI
1 0
1 0
mW
NOTES
1
The reference clock inputs are configured to accept a 1 V p-p (typical) dc offset square or sine waves centered at one-half the applied V
DD
or a 3 V TTL-level pulse input.
2
An internal 800 mV p-p differential voltage swing equates to 400 mV p-p applied to both REFCLK input pins.
3
Pipeline delays of each individual block are fixed; however, if the eight top MSBs of a tuning word are all zeros, the delay will appear longer. This is due to
insufficient phase accumulation per a system clock period to produce enough LSB amplitude to the D/A converter.
4
If a feature such as inverse sinc, which has 16 pipeline delays, can be bypassed, the total delay will be reduced by that amount.
5
The I/O Update CLK transfers data from the I/O Port Buffers to the Programming Registers. This transfer takes system clocks to perform.
6
Change in duty cycle from 1 MHz to 100 MHz with 1 V p-p sine wave input and 0.5 V threshold.
7
Represents comparator’s inherent cycle-to-cycle jitter contribution. Input signal is a 1 V, 40 MHz square wave. Measurement device Wavecrest DTS – 2075.
8
Comparator input originates from analog output section via external 7-pole elliptic LPF. Single-ended input, 0.5 V p-p. Comparator output terminated in 50
Ω
.
9
Avoid overdriving digital inputs. (Refer to equivalent circuits in Figure 1.)
10
Simultaneous operation at the maximum ambient temperature of 85
C and the maximum internal clock frequency of 200 MHz for the 80-lead LQFP, or
300 MHz for the thermally-enhanced 80-lead LQFP may cause the maximum die junction temperature of 150°C to be exceeded. Refer to the section titled Power
Dissipation and Thermal Considerations for derating and thermal management information.
11
All functions engaged.
12
All functions except inverse sinc engaged.
13
All functions except inverse sinc and digital multipliers engaged.
Specifications subject to change without notice.
°
ABSOLUTE MAXIMUM RATINGS
*
Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150
C
V
S
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . –0.7 V to +V
S
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA
Storage Temperature . . . . . . . . . . . . . . . . . . –65
°
EXPLANATION OF TEST LEVELS
Test Level
I. 100% Production Tested.
III. Sample Tested Only.
IV. Parameter is guaranteed by design and characterization testing.
V. Parameter is a typical value only.
VI. Devices are 100% production tested at 25°C and guaranteed
by design and characterization testing for industrial
operating temperature range.
°
C to +150
°
C
Operating Temperature . . . . . . . . . . . . . . . . . –40
°
C to +85
°
C
C
Maximum Clock Frequency (ASQ) . . . . . . . . . . . . . 300 MHz
Maximum Clock Frequency (AST) . . . . . . . . . . . . . 200 MHz
θ
JA
(ASQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
°
°
C/W
θ
JC
(ASQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
°
C/W
C/W
*
Absolute maximum ratings are limiting values, to be applied individually, and beyond
which the serviceability of the circuit may be impaired. Functional operability under
any of these conditions is not necessarily implied. Exposure of absolute maximum
rating conditions for extended periods of time may affect device reliability.
°
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
AD9852ASQ
–40
°
C to +85
°
C
Thermally Enhanced 80-Lead LQFP
SQ-80
AD9852AST
–40
°
C to +85
°
C
80-Lead LQFP
ST-80
AD9852/PCB
0
°
C to 70
°
C
Evaluation Board
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9852 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
–5–
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300
θ
JA
(AST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
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