ADE7752 prb

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PRELIMINARY TECHNICAL DATA
Three Phase Energy Metering IC
with Pulse Output
Preliminary Technical Data
ADE77
52
*
FEATURES
High Accuracy, Supports 50 Hz/60 Hz IEC 687/1036
Less than 0.1% Error Over a Dynamic Range of
500 to 1
Compatible with 3-phase/3-wire and 3-phase/4-wire
configurations
The ADE7752 Supplies Average Real Power on the
Frequency Outputs F1 and F2
The High Frequency Output CF Is Intended for
Calibration and Supplies Instantaneous Real Power
The Logic Output REVP indicates a Potential Miswiring or
Negative Power for each phase
Direct Drive for Electromechanical Counters and
Two Phase Stepper Motors (F1 and F2)
Proprietary ADCs and DSP Provide High Accuracy over
Large Variations in Environmental Conditions and
Time
On-Chip Power Supply Monitoring
On-Chip Creep Protection (No Load Threshold)
On-Chip Reference 2.5 V ± 8% (30 ppm/8C Typical)
with External Overdrive Capability
Single 5 V Supply, Low Power (15 mW Typical)
Low Cost CMOS Process
GENERAL DESCRIPTION
The ADE7752 is a high accuracy three phase electrical
energy measurement IC. The part specifications surpass the
accuracy requirements as quoted in the IEC1036 standard.
The only analog circuitry used in the ADE7752 is in the
ADCs and reference circuit. All other signal processing (e.g.,
multiplication, filtering and summation) is carried out in the
digital domain. This approach provides superior stability and
accuracy over extremes in environmental conditions and over
time.
The ADE7752 supplies average real power information on
the low frequency outputs F1 and F2. These logic outputs
may be used to directly drive an electromechanical counter or
interface with an MCU. The CF logic output gives instan-
taneous real power information. This output is intended to be
used for calibration purposes, or as interface with an MCU.
The ADE7752 includes a power supply monitoring circuit
on the AV
DD
supply pin. The ADE7752 will remain inactive
until the supply voltage on V
DD
reaches 4 V. If the supply falls
below 4 V, the ADE7752 will also be reset and no pulses will
be issued on F1, F2 and CF.
Internal phase matching circuitry ensures that the voltage and
current channels are phase matched. An internal no-load
threshold ensures that the ADE7752 does not exhibit any
creep when there is no load.
The ADE7752 is available in 24-lead SOIC packages.
FUNCTIONAL BLOCK DIAGRAM
RESET
VDD
17
3
IAP
IAN
5
6
16
ADC
HPF
Φ
LPF
Power
Supply
Monitor
VAP
ADC
PHASE
CORRECTION
ADE7752
IBP
IBN
7
8
15
ADC
HPF
Φ
LPF
Σ
VBP
ADC
2
DGND
PHASE
CORRECTION
19
CLKIN
20
CLKOUT
ICP
ICN
10
14
13
ADC
HPF
Φ
LPF
VCP
ADC
VN
DIGITAL-TO-FREQUENCY
CONVERTER
PHASE
CORRECTION
4k
Ω
2.5V
REF
11
12
4
18
21
22
23
24
1
*Patents pending
AGND
REF
IN/OUT
REVP
SCF
S0
S1
F2
F1
CF
REV. PrB 08/01
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
ADE7752–SPECIFICATIONS
PRELIMINARY TECHNICAL DATA
5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 10 MHz,
T
MIN
to T
MAX
= –40
C to +85
C)
Parameter
Units
Test Conditions/Comments
ACCURACY
1, 2
Measurement Error
1
on Current Channel
Voltage Channel with Full-Scale Signal (±500 mV),
+25°C
0.1
% Reading typ
Over a Dynamic Range 500 to 1
Phase Error
1
Between Channels
Line Frequency = 45 Hz to 65 Hz
(PF = 0.8 Capacitive)
±0.1
Degrees(°) max
(PF = 0.5 Inductive)
±0.1
Degrees(°) max
AC Power Supply Rejection
1
S0 = S1 = 1
Output Frequency Variation (CF)
0.01
% Reading typ
V1 = 100 mV rms, V2 = 100 mV rms, @ 50 Hz
Ripple on V
DD
of 200 mV rms @ 100 Hz
DC Power Supply Rejection
1
S0 = S1 = 1
Output Frequency Variation (CF)
0.01
% Reading typ
V1 = 100 mV rms, V2 = 100 mV rms,
V
DD
= 5 V ± 250 mV
ANALOG INPUTS
See Analog Inputs Section
Maximum Signal Levels
±0.125
V max
VAP, VBP, VCP, VN, IAP, IAN, IBP, IBN, ICP and
ICN to AGND
Input Impedance (DC)
400
kΩ min
CLKIN = 10 MHz
Bandwidth (–3 dB)
TBD
kHz typ
CLKIN/256, CLKIN = 10 MHz
ADC Offset Error
1, 2
±15
mV max
See Terminology and
Gain Error
1
±4
% Ideal typ
External 2.5 V Reference,
V1 = 125 mV dc, V2 = 125 mV dc
Gain Error Match
1
±0.2
% Ideal typ
External 2.5 V Reference
REFERENCE INPUT
REF
IN/OUT
Input Voltage Range
2.7
V max
2.5 V + 8%
2.3
V min
2.5 V – 8%
Input Impedance
3.7
kΩ min
Input Capacitance
10
pF max
ON-CHIP REFERENCE
Nominal 2.5 V
Reference Error
±200
mV max
Temperature Coefficient
30
ppm/°C typ
CLKIN
Note All Specifications for CLKIN of 10 MHz
Input Clock Frequency
15
MHz max
5
MHz min
LOGIC INPUTS
3
SCF, S0, S1, and
Input High Voltage, V
INH
2.4
V min
V
DD
= 5 V ± 5%
Input Low Voltage, V
INL
0.8
V max
V
DD
= 5 V ± 5%
Input Current, I
IN
±3
µA max
Typically 10 nA, V
IN
= 0 V to V
DD
Input Capacitance, C
IN
10
pF max
LOGIC OUTPUTS
3
F1 and F2
Output High Voltage, V
OH
I
SOURCE
= 10 mA
4.5
V min
V
DD
= 5 V
Output Low Voltage, V
OL
I
SINK
= 10 mA
0.5
V max
V
DD
= 5 V
CF and REVP
Output High Voltage, V
OH
4
V min
V
DD
= 5 V, I
SOURCE
= 5 mA
Output Low Voltage, V
OL
0.5
V max
V
DD
= 5 V, I
SINK
= 5 mA
POWER SUPPLY
For Specified Performance
V
DD
4.75
V min
5 V – 5%
5.25
V max
5 V + 5%
I
DD
4
mA typ
NOTES
1
See Terminology Section for explanation of specifications.
2
See Plots in Typical Performance Graphs.
3
Sample tested during initial release and after any redesign or process change that may affect this parameter.
Specifications subject to change without notice.
–2–
REV. PrB 08/01
(V
DD
= 5 V
PRELIMINARY TECHNICAL DATA
ADE7752
TIMING CHARACTERISTICS
1, 2
Parameter
5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 10 MHz,
T
MIN
to T
MAX
= –40
C to +85
C)
Units
Test Conditions/Comments
t
1
3
275
ms
F1 and F2 Pulsewidth (Logic High)
t
2
See Table III
sec
Output Pulse Period. See Transfer Function Section
t
3
1/2 t
2
sec
Time Between F1 Falling Edge and F2 Falling Edge
t
4
3, 4
90
ms
CF Pulsewidth (Logic High)
t
5
See Table IV
sec
CF Pulse Period. See Transfer Function Section
t
6
CLKIN/4
sec
Minimum Time Between F1 and F2 Pulse
NOTES
1
Sample tested during initial release and after any redesign or process change that may affect this parameter.
2
See Figure 1.
3
The pulsewidths of F1, F2 and CF are not fixed for higher output frequencies. See Frequency Outputs Section.
4
The CF pulse is always 1 µs in the high frequency mode. See Frequency Outputs section and Table IV.
Specifications subject to change without notice.
t
1
ORDERING GUIDE
F1
Model
Package Description
Package Option
t
6
t
2
ADE7752AR
SOIC Package
R-24
EVAL-ADE7752EB ADE7752 Evaluation
Board
F2
t
3
t
4
t
5
CF
Figure 1. Timing Diagram for Frequency Outputs
REV. PrB 08/01
3–
(V
DD
= 5 V
PRELIMINARY TECHNICAL DATA
ADE7752
ABSOLUTE MAXIMUM RATINGS*
(T
A
= +25°C unless otherwise noted)
V
DD
to AGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
V
DD
to DGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Analog Input Voltage to AGND
VAP, VBP, VCP, VN, IAP, IAN, . . . . . . . . . . . . . . . . . .
IBP, IBN, ICP and ICN . . . . . . . . . . . . . –6 V to +6 V
Reference Input Voltage to AGND –0.3 V to V
DD
+ 0.3 V
Digital Input Voltage to DGND . –0.3 V to V
DD
+ 0.3 V
Digital Output Voltage to DGND –0.3 V to V
DD
+ 0.3 V
Operating Temperature Range
Industrial . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C
24-Lead SOIC, Power Dissipation . . . . . . . . . TBD mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . 250 °C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . +220°C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADE7752 features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
TERMINOLOGY
MEASUREMENT ERROR
The error associated with the energy measurement made by
the ADE7752 is defined by the following formula:
ADC OFFSET ERROR
This refers to the dc offset associated with the analog inputs
to the ADCs. It means that with the analog inputs connected
to AGND the ADCs still see an analog input signal of 1 mV
to 10 mV, depending on gain setting. However, as the HPF
is always present, the offset is removed from the current
channel and the power calculation is not affected by this
offset.
Percentage
Error
=
Energy
Registered
by
the
ADE7752
–
True
Energy
×
100
%
True
Energy
PHASE ERROR BETWEEN CHANNELS
The HPF (High Pass Filter) in the current channel has a
phase lead response. To offset this phase response and
equalize the phase response between channels a phase correc-
tion network is also placed in the current channel. The phase
correction network ensures a phase match between the
current channels and voltage channels to within ±0.1° over a
range of 45Hz to 65Hz and ±0.2° over a range 40Hz to 1kHz.
This phase mismatch between the voltage and the current
channels can be further reduced with the phase calibration
register in each phase.
See Figures 18 and 19.
GAIN ERROR
The gain error of the ADE7752 is defined as the difference
between the measured output frequency (minus the offset) and
the ideal output frequency. The difference is expressed as a
percentage of the ideal frequency. The ideal frequency is
obtained from the ADE7752 transfer function—see
Transfer
Function section
.
POWER SUPPLY REJECTION
This quantifies the ADE7752 measurement error as a per-
centage of reading when the power supplies are varied.
For the ac PSR measurement a reading at nominal supplies
(5 V) is taken. A 200 mV rms/100 Hz signal is then
introduced onto the supplies and a second reading obtained
under the same input signal levels. Any error introduced is
expressed as a percentage of reading—see
Measurement Error
definition
.
For the dc PSR measurement a reading at nominal supplies
(5 V) is taken. The supply is then varied ±5% and a second
reading is obtained with the same input signal levels. Any
error introduced is again expressed as a percentage of
reading.
–4–
REV. PrB 08/01
PRELIMINARY TECHNICAL DATA
ADE7752
PIN FUNCTION DESCRIPTION
Pin No.
MNEMONIC
DESCRIPTION
1
C F
Calibration Frequency Logic Output. The CF logic output gives instantaneous real
power information. This output is intended to be used for calibration purposes. Also see
SCF pin description.
2
DGND
This provides the ground reference for the digital circuitry in the ADE7752, i.e. multi-
plier, filters and digital-to-frequency converter. Because the digital return currents in
the ADE7752 are small, it is acceptable to connect this pin to the analog ground plane
of the whole system - see
Applications Information
. However high bus capacitance on the
DOUT pin may result in noisy digital current which could affect performance.
3
V
DD
Power supply. This pin provides the supply voltage for the digital circuitry in the
ADE7752. The supply voltage should be maintained at 5V ± 5% for specified opera-
tion. This pin should be decoupled to DGND with a 10µF capacitor in parallel with a
ceramic 100nF capacitor.
4
REVP
This logic output will go logic high when negative power is detected on any of the three
phase inputs, i.e., when the phase angle between the voltage and the current signals is
greater that 90°. This output is not latched and will be reset when positive power is
once again detected. The output will go high or low at the same time as a pulse is is-
sued on CF.
5,6;
I
AP
, I
AN
;
Analog inputs for current channel. This channel is intended for use with the current
7,8;
I
BP
, I
BN
;
transducer and is referenced in this document as the current channel. These inputs are
9,10
I
CP
, I
CN
fully differential voltage inputs with maximum differential input signal levels of
±0.125V -See
Analog Inputs
. Both inputs have internal ESD protection circuitry, and in
addition an overvoltage of ±6V can be sustained on these inputs without risk of perma
nent damage.
11
AGND
This pin provides the ground reference for the analog circuitry in the ADE7754, i.e.
ADCs, temperature sensor, and reference. This pin should be tied to the analog ground
plane or the quietest ground reference in the system. This quiet ground reference
should be used for all analog circuitry, e.g. anti aliasing filters, current and voltage
transducers etc. In order to keep ground noise around the ADE7754 to a minimum, the
quiet ground plane should only connected to the digital ground plane at one point. It is
acceptable to place the entire device on the analog ground plane - see
Applications Informa-
tion.
12
REF
IN/OUT
This pin provides access to the on-chip voltage reference. The on-chip reference has a
nominal value of 2.5V ± 8% and a typical temperature coefficient of 30ppm/°C. An
external reference source may also be connected at this pin. In either case this pin
should be decoupled to AGND with a 1µF ceramic capacitor.
13-16
V
N
,V
CP
,
Analog inputs for the voltage channel. This channel is intended for use with the voltage
V
BP
, V
AP
transducer and is referenced as the voltage channel in this document. These inputs are
single-ended voltage inputs with maximum signal level of ±0.125V with respect to V
N
for specified operation. All inputs have internal ESD protection circuitry, and in addi
tion an over voltage of ±6V can be sustained on these inputs without risk of permanent
damage.
17
RESET
Reset pin for the ADE7752. A logic low on this pin will hold the ADCs and digital
circuitry (including the Serial Interface) in a reset condition.
18
S C F
Select Calibration Frequency. This logic input is used to select the frequency on the
calibration output CF. Table IV shows how the calibration frequencies are selected.
REV. PrB 08/01
–5–
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