ADE7754 PrE

[ Pobierz całość w formacie PDF ]
PRELIMINARY TECHNICAL DATA
Three Phase Multi-Function
Energy Metering IC with Serial Port
PreliminaryTechnical Data
ADE7754*
FEATURES
High Accuracy, supports IEC 687/1036
Compatible with 3-phase/3-wire, 3-phase/4-wire
and any type of 3-phase services
Less than 0.1% error over a dynamic range of 500 to 1
The ADE7754 supplies Active Energy, Apparent Energy,
Voltage rms, Current rms and Sampled Waveform Data.
Digital Power, Phase & Input Offset Calibration.
An On-Chip temperature sensor (±3°C typ. after calibration)
On-Chip user Programmable thresholds for line voltage
SAG and overdrive detections.
A SPI compatible Serial Interface with Interrupt Request line
(IRQ).
A pulse output with programmable frequency
Proprietary ADCs and DSP provide high accuracy over large
variations in environmental conditions and time.
Reference 2.5V±8% (Drift 30 ppm/°C typical)
with external overdrive capability
Single 5V Supply, Low power (15mW typical)
The ADE7754 provides different solutions to measure Active
and Apparent Energy from the six analog inputs thus en-
abling the use of the ADE7754 in various Power meter
services as 3-phase 4-wire, 3-phase 3-wire but also 4-wire
delta.
In addition to RMS calculation, Real and Apparent power
informations, the ADE7754 provides system calibration
features for each phase, i.e., channel offset correction, phase
calibration and power calibration. The CF logic output gives
instantaneous real power information.
The ADE7754 has a waveform sample register which enables
access to ADC outputs. The part also incorporates a detec-
tion circuit for short duration low or high voltage variations.
The voltage threshold levels and the duration (no. of half line
cycles) of the variation are user programmable.
A zero crossing detection is synchronized which the zero
crossing point of the line voltage of each of the three phases.
This information is used to measure each line’s Period. It is
also used internally to the chip in the Line Active Energy and
Line Apparent Energy accumulation modes. This permits
faster and more accurate calibration of the power calcula-
tions. This signal is also useful for synchronization of relay
switching.
Data is read from the ADE7754 via the SPI serial interface.
The interrupt request out
p
ut (
) is an open drain, active
low logic output. The IRQ output will go active low when one
or more interrupt events have occurred in the ADE7754. A
status register will indicate the nature of the interrupt.
The ADE7754 is available in a 24-lead SOIC package.
GENERAL DESCRIPTION
The ADE7754 is a high accuracy three-phase electrical
energy measurement IC with a serial interface and a pulse
output. The ADE7754 incorporates second order sigma-
delta ADCs, reference circuitry, temperature sensor, and all
the signal processing required to perform Active Energy
measurement, Apparent Energy measurement and rms calcu-
lation.
FUNCTIONAL BLOCK DIAGRAM
RESET
17
AVDD
4
AVGAIN
AVRMSOS
ADE7754
Σ
Power
Supply
Monitor
AIRMSOS
AVAG
PGA1
AAPGAIN
Σ
IAP
IAN
VAP
5
6
16
PGA2
ADC
HPF
Φ
APHCAL
LPF2
Σ
AAPOS
ADC
AWG
BVGAIN
BVRMSOS
Σ
BIRMSOS
BVAG
Σ
CFNUM
PGA1
BAPGAIN
Σ
IBP
IBN
VBP
7
8
15
ADC
Σ
BAPOS
Σ
DFC
1
CF
PGA2
HPF
LPF2
ADC
Φ
BPHCAL
BWG
CFDEN
CVRMSOS
Σ
3
DVDD
2
DGND
CVAG
CIRMSOS
CVGAIN
CAPGAIN
19
CLKIN
PGA1
Σ
20
CLKOUT
ICP
ICN
VCP
ADC
WDIV
VADIV
Σ
CAPOS
10
14
13
PGA2
HPF
LPF2
ADC
Φ
CPHCAL
CWG
VN
ADE7754 REGISTERS &
SERIAL INTERFACE
2.5V
REF
4k
Ω
TEMP
SENSOR
ADC
* Patents pending.
11
12
22
24
23
21
18
AGND
REF
IN/OUT
DIN
DOUT
SCLK
CS IRQ
REV. PrE 09/01
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
ADE7754–SPECIFICATIONS
PRELIMINARY TECHNICAL DATA
(AVDD = DVDD = 5V±5%, AGND = DGND = 0V, On-Chip Reference,
CLKIN=10MHz, TMIN to TMAX = -40ºC to +85ºC)
Parameters
Units
Test Conditions/Comments
ACCURACY
Measurement Error (per phase)
0.1
% typ
Over a dynamic range of 500 to 1
Phase Error Between Channels
Line Frequency = 45Hz to 65Hz
(PF=0.8 capacitive)
±0.05
º max
Phase Lead 37º
(PF=0.5 inductive)
±0.05
º max
Phase Lag 60º
AC Power Supply Rejection
1
Output Frequency Variation
0.01
% typ
V1P = V2P = V3P = ±100mV rms
DC Power Supply Rejection
1
Output Frequency Variation
0.01
% typ
V1P = V2P = V3P = ±100mV rms
ANALOG INPUTS
Maximum Signal Levels
±500
mV peak max
Differential input
Input Impedance (DC)
400
k min
Bandwidth (-3dB)
14
kHz typ
ADC Offset Error
1
10
mV max
Uncalibrated error, see Terminology for detail
Gain Error
1
± 4
% typ
External 2.5V reference
Gain Error Match
1
± 3
% typ
External 2.5V reference
REFERENCE INPUT
REF
IN/OUT
Input Voltage Range
2.7
V max
2.5V +8%
2.3
V min
2.5V -8%
Input Impedance
4
kW min
Input Capacitance
10
pF max
TEMPERATURE SENSOR
±2
ºC
Calibrated DC offset
ON-CHIP REFERENCE
Reference Error
±200
mV max
Temperature Coefficient
30
ppm/ºC typ
CLKIN
Input Clock Frequency
15
MHz max
5
MHz min
LOGIC INPUTS
, DIN, SCLK CLKIN
and
2.4
V min
DV
DD
=5V ± 5%
Input Low Voltage, V
INL
0.8
V max
DV
DD
=5V ± 5%
Input Current, I
IN
±3
mA max
Typical 10nA, Vin=0V to DV
DD
Input Capacitance, C
IN
10
pF max
, DOUT and CLKOUT
Output High Voltage, V
OH
4
V min
DVDD=5V ± 5%
Output Low Voltage, V
OL
1
V max
DVDD=5V ± 5%
POWER SUPPLY
For specified performance
AV
DD
4.75
V min
5V - 5%
5.25
V max
5V +5%
DV
DD
4.75
V min
5V - 5%
5.25
V max
5V +5%
AI
DD
TBD
mA max
DI
DD
TBD
mA max
NOTES:
1. See Terminology section for explanation of specifications.
2. See plots in Typical Performance Graph.
3. Specification subject to change without notice.
ORDERING GUIDE
MODEL
PACKAGE OPTION
*
ADE7754AR
SO-24
EVAL-ADE7754EB
ADE7754 Evaluation Board
REV. PrE 09/01
–2–
Input High Voltage, V
INH
LOGIC OUTPUTS
CF,
PRELIMINARY TECHNICAL DATA
ADE7754
ADE7754 TIMING CHARACTERISTICS
1,2
Parameter
(AV
DD
= DV
DD
= 5V ± 5%, AGND = DGND = 0V, On-Chip Reference,
CLKIN = 10MHz XTAL, TMIN to TMAX = -40°C to +85°C)
Units
Test Conditions/Comments
Write timing
t
1
50
ns (min) CS falling edge to first SCLK falling edge
t
2
50
ns (min) SCLK logic high pulse width
t
3
50
ns (min) SCLK logic low pulse width
t
4
10
ns (min) Valid Data Set up time before falling edge of SCLK
t
5
5
ns (min) Data Hold time after SCLK falling edge
t
6
900
ns (min) Minimum time between the end of data byte transfers.
t
7
50
ns (min) Mi
n
imum time between byte transfers during a serial write.
t
8
100
ns (min) CS Hold time after SCLK falling edge.
Read timing
t
9
1
µs (min) Minimum time between read command (i.e. a write to Communication
Register) and data read.
t
10
50
ns (min) Minimum time between data byte transfers during a multibyte read.
t
11
3
30
ns (min) Data access time after SCLK rising edge following a write to the
Communications Register
t
12
4
100
ns (max) Bus relinquish time after falling edge of SCLK.
10
ns (min)
t
13
4
100
ns (max) Bus relinquish time after rising edge of
.
10
ns (min)
NOTES
1
Sample tested during initial release and after any redesign or process change that may
affect this parameter. All input signals are specified with tr = tf = 5ns (10% to 90%)
and timed from a voltage level of 1.6V.
2
See timing diagram below and Serial Interface section of this data sheet.
3
Measured with the load circuit in Figure 1 and defined as the time required for the
output to cross 0.8V or 2.4V.
4
Derived from the measured time taken by the data outputs to change 0.5V when
loaded with the circuit in Figure 1. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50pF capacitor. This means that
the time quoted in the timing characteristics is the true bus relinquish time of the
part and is independent of the bus loading.
I
OL
200 µA
TO
OUTPUT
PIN
+2.1V
C
L
50pF
1.6 mA
I
OH
Figure 1 - Load Circuit for Timing Specifications
Serial Write Timing
t
8
CS
t
1
t
2
t
3
t
6
SCLK
t
7
t
7
t
4
t
5
DIN
1
0
A5
A4 A3 A2 A1 A0
DB7
DB0
DB7
DB0
Command Byte
Most Significant Byte
Least Significant Byte
Serial Read Timing
CS
t
1
t
9
t
10
t
14
SCLK
DIN
00
A5
A4 A3 A2 A1 A0
t
11
t
12
t
13
DOUT
DB7
DB0
DB7
DB0
Command
Byte
Most Significant
Byte
Least Significan
t
Byte
REV. PrE 09/01
–3–
PRELIMINARY TECHNICAL DATA
ADE7754
ABSOLUTE MAXIMUM RATINGS*
(T
A
= +25°C unless otherwise noted)
AV
DD
to AGND . . . . . . . . . . . . . . . . . . . . . –0.3V to +7V
DV
DD
to DGND . . . . . . . . . . . . . . . . . . . . –0.3V to +7V
DV
DD
to AV
DD
. . . . . . . . . . . . . . . . . . . . . –0.3V to +0.3V
Analog Input Voltage to AGND
I
AP
,I
AN
,I
BP
,I
BN
,I
CP
,I
CN
,V
AP
,V
BP
,V
CP
,V
N
. –6V to +6V
Reference Input Voltage to AGND –0.3V to AV
DD
+0.3V
Digital Input Voltage to DGND . –0.3V to DV
DD
+0.3V
Digital Output Voltage to DGND –0.3V to DV
DD
+0.3V
Operating Temperature Range
Industrial . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C
24-Lead SOIC, Power Dissipation . . . . . . . . . TBD mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . 53°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . +220°C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADE7754 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
Terminology
MEASUREMENT ERROR
The error associated with the energy measurement made by
the ADE7754 is defined by the following formula:
Any error introduced is again expressed as a percentage of
reading.
Percentage
Error
=
ADC OFFSET ERROR
This refers to the DC offset associated with the analog inputs
to the ADCs. It means that with the analog inputs connected
to AGND the ADCs still see a dc analog input signal. The
magnitude of the offset depends on the gain and input range
selection - see characteristic curves. However, when HPFs
are switched on the offset is removed from the current
channels and the power calculation is not affected by this
offset.
Energy
registered
by
7754
Energy
−
True
Energy
×
100
%
True
PHASE ERROR BETWEEN CHANNELS
The HPF (High Pass Filter) in the current channel has a
phase lead response. To offset this phase response and
equalize the phase response between channels a phase correc-
tion network is also placed in the current channel. The phase
correction network ensures a phase match between the
current channels and voltage channels to within ±0.1° over a
range of 45Hz to 65Hz and ±0.2° over a range 40Hz to 1kHz.
This phase mismatch between the voltage and the current
channels can be further reduced with the phase calibration
register in each phase.
GAIN ERROR
The gain error in the ADE7754 ADCs, is defined as the
difference between the measured ADC output code (minus
the offset) and the ideal output code - see
Current Channel ADC
&
Voltage Channel ADC
. The difference is expressed as a
percentage of the ideal code.
POWER SUPPLY REJECTION
This quantifies the ADE7754 measurement error as a per-
centage of reading when the power supplies are varied.
For the AC PSR measurement a reading at nominal supplies
(5V) is taken. A second reading is obtained with the same
input signal levels when an ac (175mVrms/100Hz) signal is
introduced onto the supplies. Any error introduced by this ac
signal is expressed as a percentage of reading—see Measure-
ment Error definition above.
For the DC PSR measurement a reading at nominal supplies
(5V) is taken. A second reading is obtained with the same
input signal levels when the power supplies are varied ±5%.
GAIN ERROR MATCH
The Gain Error Match is defined as the gain error (minus the
offset) obtained when switching between a gain of 1, 2 or 4.
It is expressed as a percentage of the output ADC code
obtained under a gain of 1.
– 4 –
REV. PrE 09/01
ADE
PRELIMINARY TECHNICAL DATA
Characteristic Curves–
ADE7754
TBD
TBD
TPC 1. ADE7754 Error as a % of reading (Gain=1)
TPC 2. ADE7754 Error as a % of reading (Gain=2)
TBD
TBD
TPC 4. ADE7754 Error as a % of reading (Gain=4)
TPC 5. AC PSRR as a function of power
supply ripple (Gain=1)
TBD
TBD
TPC 7. AC PSRR as a function of power
supply ripple (Gain=2)
TPC 8. AC PSRR as a function of power
supply ripple (Gain=4)
REV. PrE 09/01
– 5 –
[ Pobierz całość w formacie PDF ]