ADE7759 0

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a
Active Energy Metering IC with
di/dt Sensor Interface
ADE7759
*
FEATURES
High Accuracy, Supports IEC 687/1036
On-Chip Digital Integrator Allows Direct Interface with
Current Sensors with di/dt Output Such as Rogowski Coil
Less Than 0.1% Error over a Dynamic Range of 1000 to 1
On-Chip User-Programmable Threshold for Line Voltage
SAG Detection and PSU Supervisory
The ADE7759 Supplies Sampled Waveform Data and
Active Energy (40 Bits)
Digital Power, Phase and Input DC Offset Calibration
On-Chip Temperature Sensor (Typical 1 LSB/
C Resolution)
between the current and the voltage channels. The integrator
can be switched off if the ADE7759 is used with conventional
current sensors.
The ADE7759 contains a sampled Waveform register and an Active
Energy register capable of holding at least 11.53 seconds of accumu-
lated power at full ac load. Data is read from the ADE7759 via the
serial interface. The ADE7759 also provides a pulse output (CF)
with frequency that is proportional to the active power.
In addition to active power information, the ADE7759 also
provides various system calibration features, i.e., channel offset
correction, phase calibration, and power offset correction. The
part also incorporates a detection circuit for short duration
voltage drop (SAG). The voltage threshold and the duration (in
number of half-line cycles) of the drop are user programmable.
An open drain logic output (
SAG
) goes active low when a sag
event occurs.
A zero crossing output (ZX) produces an output that is synchro-
nized to the zero crossing point of the line voltage. This output
can be used to extract timing or frequency information from the
line. The signal is also used internally to the chip in the line
cycle energy accumulation mode; i.e., the number of half-line
cycles in which the energy accumulation occurs can be con-
trolled. Line cycle energy accumulation enables a faster and
more precise energy accumulation and is especially useful dur-
ing calibration. This signal is also useful for synchronization of
relay switching with a voltage zero crossing.
The interrupt request output is an open drain, active low logic
output. The Interrupt Status Register indicates the nature of the
interrupt, and the Interrupt Enable Register controls which
event produces an output on the
IRQ
pin. The ADE7759 is
available in a 20-lead SSOP package.
SPI-Compatible Serial Interface
Pulse Output with Programmable Frequency
Interrupt Request Pin (IRQ) and IRQ Status Register
Proprietary ADCs and DSP provide High Accuracy over
Large Variations in Environmental Conditions and Time
Reference 2.4V
8% (20 ppm/
C Typical) with External
Overdrive Capability
Single 5V Supply, Low Power Consumption (25mW
Typical)
ADCs, a digital integrator (on CH1),
reference circuitry, temperature sensor, and all the signal processing
required to perform active power and energy measurement.
An on-chip digital integrator allows direct interface to di/dt
current sensors such as a Rogowski coil. The digital integrator
eliminates the need for an external analog integrator and pro-
vides excellent long-term stability and precise phase matching
Σ
-
∆
FUNCTIONAL BLOCK DIAGRAM
AVDD
RESET
DVDD
DGND
ADE7759
ZX
MULTIPLIER
INTEGRATOR
MULTIPLIER
V1P
V1N
ADC
dt
LPF2
SAG
HPF1
TEMP
SENSOR
APGAIN[11:0]
APOS[15:0]
PHCAL[7:0]
V2P
ADC
DFC
V2N
2.4V
REFERENCE
4k
REGISTERS AND
SERIAL INTERFACE
CFNUM[11:0]
CFDEN[11:0]
CF
LPF1
AGND
REF
IN/OUT
DIN DOUT SCLK
CS IRQ
CLKIN CLKOUT
*
U.S. Patents 5,745,323; 5,760,617; 5,862,069; 5,872,469; others pending.
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
GENERAL DESCRIPTION
The ADE7759 is an accurate active power and energy measurement
IC with a serial interface and a pulse output. The ADE7759 incor-
porates two second order
REV. 0
ADE7759
TABLE OF CONTENTS
FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1
FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . 1
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . 5
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 6
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 7
TERMINOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
MEASUREMENT ERROR . . . . . . . . . . . . . . . . . . . . . . . . . 8
PHASE ERROR BETWEEN CHANNELS . . . . . . . . . . . . . 8
POWER SUPPLY REJECTION . . . . . . . . . . . . . . . . . . . . . . 8
ADC OFFSET ERROR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
GAIN ERROR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
GAIN ERROR MATCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
TYPICAL PERFORMANCE CHARACTERISTICS (TPC) . . 9
TEST CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
ANALOG INPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
di/dt CURRENT SENSOR AND DIGITAL
INTEGRATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
ZERO CROSSING DETECTION . . . . . . . . . . . . . . . . . . . 13
LINE VOLTAGE SAG DETECTION . . . . . . . . . . . . . . . . 14
Sag Level Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
POWER SUPPLY MONITOR . . . . . . . . . . . . . . . . . . . . . . 14
INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Using the ADE7759 Interrupts with an MCU . . . . . . . . . 15
Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
TEMPERATURE MEASUREMENT . . . . . . . . . . . . . . . . 16
ANALOG-TO-DIGITAL CONVERSION . . . . . . . . . . . . . 16
Antialias Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
ADC Transfer Function . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Reference Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
CHANNEL 1 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Channel 1 ADC Gain Adjust . . . . . . . . . . . . . . . . . . . . . . 18
Channel 1 Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
CHANNEL 1 AND CHANNEL 2 WAVEFORM
SAMPLING MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
CHANNEL 2 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Channel 2 Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
PHASE COMPENSATION . . . . . . . . . . . . . . . . . . . . . . . . 19
ACTIVE POWER CALCULATION . . . . . . . . . . . . . . . . . 20
ENERGY CALCULATION . . . . . . . . . . . . . . . . . . . . . . . . 21
Integration Time under Steady Load . . . . . . . . . . . . . . . . 22
POWER OFFSET CALIBRATION . . . . . . . . . . . . . . . . . . 22
ENERGY-TO-FREQUENCY CONVERSION . . . . . . . . . 22
LINE CYCLE ENERGY ACCUMULATION MODE . . . 24
CALIBRATING THE ENERGY METER . . . . . . . . . . . . . 24
Calculating the Average Active Power . . . . . . . . . . . . . . . 24
Calibrating the Frequency at CF . . . . . . . . . . . . . . . . . . . 25
Energy Meter Display . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
CLKIN FREQUENCY . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
SUSPENDING THE ADE7759 FUNCTIONALITY . . . . 26
APPLICATION INFORMATION . . . . . . . . . . . . . . . . . . . 26
SERIAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Serial Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Serial Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
CHECKSUM REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . 28
REGISTER DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . 29
Communications Register . . . . . . . . . . . . . . . . . . . . . . . . 29
Mode Register (06H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Interrupt Status Register (04H) . . . . . . . . . . . . . . . . . . . . 31
Reset Interrupt Status Register (05H) . . . . . . . . . . . . . . . 31
CH1OS Register (08H) . . . . . . . . . . . . . . . . . . . . . . . . . . 32
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 32
–2–
REV. 0
ADE7759
SPECIFICATIONS
1
Parameter
(AV
DD
= DV
DD
= 5 V
5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 3.579545 MHz XTAL,
T
MIN
to T
MAX
= –40
C to +85
C unless otherwise noted.)
Spec Unit
Test Conditions/Comments
ENERGY MEASUREMENT ACCURACY
Measurement Bandwidth
14
kHz
CLKIN = 3.579545 MHz
Measurement Error
1
on Channel 1
Channel 2 = 300 mV rms/60 Hz, Gain = 1
Channel 1 Range = 0.5 V Full-Scale
Gain = 1
0.1
% typ
Over a Dynamic Range 1000 to 1
Gain = 2
0.1
% typ
Over a Dynamic Range 1000 to 1
Gain = 4
0.1
% typ
Over a Dynamic Range 1000 to 1
Gain = 8
0.1
% typ
Over a Dynamic Range 1000 to 1
Gain = 16
0.2
% typ
Over a Dynamic Range 1000 to 1
Channel 1 Range = 0.25 V Full-Scale
Gain = 1
0.1
% typ
Over a Dynamic Range 1000 to 1
Gain = 2
0.1
% typ
Over a Dynamic Range 1000 to 1
Gain = 4
0.1
% typ
Over a Dynamic Range 1000 to 1
Gain = 8
0.2
% typ
Over a Dynamic Range 1000 to 1
Gain = 16
0.2
% typ
Over a Dynamic Range 1000 to 1
Channel 1 Range = 0.125 V Full-Scale
Gain = 1
0.1
% typ
Over a Dynamic Range 1000 to 1
Gain = 2
0.1
% typ
Over a Dynamic Range 1000 to 1
Gain = 4
0.2
% typ
Over a Dynamic Range 1000 to 1
Gain = 8
0.2
% typ
Over a Dynamic Range 1000 to 1
Gain = 16
0.4
% typ
Over a Dynamic Range 1000 to 1
Phase Error
1
between Channels
±
0.05
°
max
Line Frequency = 45 Hz to 65 Hz, HPF on
AC Power Supply Rejection
1
AV
DD
= DV
DD
= 5 V + 175 mV rms/120 Hz
Output Frequency Variation (CF)
0.2
% typ
Channel 1 = 20 mV rms/60 Hz, Gain = 16, Range = 0.5 V
Channel 2 = 300 mV rms/60 Hz, Gain = 1
DC Power Supply Rejection
1
AV
DD
= DV
DD
= 5 V
±
250 mV dc
Output Frequency Variation (CF)
±
0.3
% typ
Channel 1 = 20 mV rms/60 Hz, Gain = 16, Range = 0.5 V
Channel 2 = 300 mV rms/60 Hz, Gain = 1
ANALOG INPUTS
See Analog Inputs Section
Maximum Signal Levels
±0.5
V max
V1P, V1N, V2N, and V2P to AGND
Input Impedance (DC)
390
kΩ min
Bandwidth
14
kHz
CLKIN/256, CLKIN = 3.579545 MHz
Gain Error
1, 3
External 2.5 V Reference, Gain = 1 on Channel 1 and 2
Channel 1
Range = 0.5 V Full-Scale
±4
% typ
V1 = 0.5 V dc
Range = 0.25 V Full-Scale
±4
% typ
V1 = 0.25 V dc
Range = 0.125 V Full-Scale
±4
% typ
V1 = 0.125 V dc
Channel 2
±4
% typ
V2 = 0.5 V dc
Gain Error Match
1
External 2.5 V Reference
Channel 1
Range = 0.5 V Full-Scale
±0.3
% typ
Gain = 1, 2, 4, 8, 16
Range = 0.25 V Full-Scale
±0.3
% typ
Gain = 1, 2, 4, 8, 16
Range = 0.125 V Full-Scale
±0.3
% typ
Gain = 1, 2, 4, 8, 16
Channel 2
±0.3
% typ
Gain = 1, 2, 4, 8, 16
Offset Error
1
Channel 1
±10
mV max Gain = 1
Channel 2
±10
mV max Gain = 1
WAVEFORM SAMPLING
Sampling CLKIN/128, 3.579545 MHz/128 = 27.9 kSPS
Channel 1
See Channel 1 Sampling
Signal-to-Noise plus Distortion
62
dB typ
150 mV rms/60 Hz, Range = 0.5 V, Gain = 2
Bandwidth (–3 dB)
14
kHz
CLKIN = 3.579545 MHz
Channel 2
See Channel 2 Sampling
Signal-to-Noise plus Distortion
52
dB typ
150 mV rms/60 Hz, Gain = 2
Bandwidth (–3 dB)
156
Hz
CLKIN = 3.579545 MHz
REV. 0
–3–
ADE7759–SPECIFICATIONS
(continued)
Parameter
Spec Unit
Test Conditions/Comments
REFERENCE INPUT
REF
IN/OUT
Input Voltage Range
2.6
V max
2.4 V + 8%
2.2
V min
2.4 V – 8%
Input Capacitance
10
pF max
ON-CHIP REFERENCE
Nominal 2.4 V at REF
IN/OUT
Pin
Reference Error
±
200 mV max
Current Source
10
µ
A max
Output Impedance
4
k
Ω
min
Temperature Coefficient
20
ppm/
°
C typ
CLKIN
Note All Specifications CLKIN of 3.579545 MHz
Input Clock Frequency
4
MHz max
1
MHz min
LOGIC INPUTS
RESET
, DIN, SCLK, CLKIN, and
CS
Input High Voltage, V
INH
2.4
V min
DV
DD
= 5 V ± 5%
Input Low Voltage, V
INL
0.8
V max
DV
DD
= 5 V ± 5%
Input Current, I
IN
±3
µA max
Typically 10 nA, V
IN
= 0 V to DV
DD
Input Capacitance, C
IN
10
pF max
LOGIC OUTPUTS
SAG
and
IRQ
Open Drain Outputs, 10 k
Ω
pull-up resistor
Output High Voltage, V
OH
4
V min
I
SOURCE
= 5 mA
Output Low Voltage, V
OL
0.4
V max
I
SINK
= 0.8 mA
ZX and DOUT
Output High Voltage, V
OH
4
V min
I
SOURCE
= 5 mA
Output Low Voltage, V
OL
0.4
V max
I
SINK
= 0.8 mA
CF
Output High Voltage, V
OH
4
V min
I
SOURCE
= 5 mA
Output Low Voltage, V
OL
1
V max
I
SINK
= 7 mA
POWER SUPPLY
For Specified Performance
AV
DD
4.75
V min
5 V – 5%
5.25
V max
5 V + 5%
DV
DD
4.75
V min
5 V – 5%
5.25
V max
5 V + 5%
AI
DD
3
mA max
Typically 2.0 mA
DI
DD
4
mA max
Typically 3.0 mA
NOTES
1
See Terminology section for explanation of specifications.
2
See plots in Typical Performance Characteristics.
3
See Analog Inputs section.
Specifications subject to change without notice.
–4–
REV. 0
ADE7759
TIMING CHARACTERISTICS
1, 2
Parameter
5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 3.579545 MHz
XTAL, T
MIN
to T
MAX
= –40
C to +85
C unless otherwise noted.)
A, B Versions
Unit
Test Conditions/Comments
Write Timing
t
1
20
ns (min)
CS
Falling Edge to First SCLK Falling Edge
t
2
150
ns (min)
SCLK Logic High Pulsewidth
t
3
150
ns (min)
SCLK Logic Low Pulsewidth
t
4
10
ns (min)
Valid Data Setup Time Before Falling Edge of SCLK
t
5
5
ns (min)
Data Hold Time After SCLK Falling Edge
t
6
6.4
µs (min)
Minimum Time between the End of Data Byte Transfers
t
7
4
µs (min)
Minimum Time between Byte Transfers During a Serial Write
t
8
100
ns (min)
CS
Hold Time After SCLK Falling Edge
Read Timing
t
9
4
µs (min)
Minimum Time between Read Command (i.e., a Write to Communications
Register) and Data Read
t
10
4
µs (min)
Minimum Time between Data Byte Transfers During a Multibyte Read
t
11
3
30
ns (min)
Data Access Time After SCLK Rising Edge following a Write to the Communi-
cations Register
t
12
4
100
ns (max) Bus Relinquish Time After Falling Edge of SCLK
10
ns (min)
t
13
4
100
ns (max) Bus Relinquish Time After Rising Edge of
CS
10
ns (min)
NOTES
1
Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5 ns
(10% to 90%) and timed from a voltage level of 1.6 V.
2
See Figures 2 and 3 and Serial Interface section of this data sheet.
3
Measured with the load circuit in Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.
4
Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 1. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the timing characteristics is the true bus relinquish time of
the part and is independent of the bus loading.
200
A
I
OL
TO
OUTPUT
PIN
C
L
50pF
2.1V
1.6mA
I
OH
Figure 1. Load Circuit for Timing Specifications
t
8
CS
t
1
t
2
t
3
t
7
t
7
t
6
SCLK
t
4
t
5
DIN
1
00
A4 A3 A2 A1 A0
DB7
DB0
DB7
DB0
COMMAND BYTE
MOST SIGNIFICANT BYTE
LEAST SIGNIFICANT BYTE
Figure 2. Serial Write Timing
CS
t
1
t
9
t
10
t
13
SCLK
DIN
000
A4 A3 A2 A1 A0
t
11
t
11
t
12
DOUT
DB7
DB0
DB7
DB0
COMMAND BYTE
MOST SIGNIFICANT BYTE
LEAST SIGNIFICANT BYTE
Figure 3. Serial Read Timing
REV. 0
–5–
(AV
DD
= DV
DD
= 5 V
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