ADM1060 prf

[ Pobierz całość w formacie PDF ]
Communications System
Supervisory/Sequencing Circuit
Preliminary Technical Data
ADM1060
FEATURES
Faults detected on 7 independent supplies
•
1 High Voltage supply (up to 14.4V)
•
4 Positive Voltage Only Supplies (up to 6V)
•
2 Positive/Negative Voltage supplies (up to +6V OR
down to -6V)
Watchdog Detector Input- Timeout delay
programmable from 200ms to 12.8sec
4 General Purpose Logic Inputs
Programmable Logic Block- combinatorial and
sequencing logic control of all inputs and outputs
9 Programmable Output Drivers
•
Open Collector (external resistor required)
•
Open Collector with internal pull-up to V
DD
•
Fast Internal pull-up to V
DD
•
Open Collector with internal pull-up to VPn
•
Fast Internal pull-up to VPn
•
Internally charge pumped high drive (for use with
external N- channel FETS- PDO’s 1 to 4 only)
EEPROM- 512 Bytes
Industry Standard 2- Wire Bus Interface (SMBus)
overvoltage or out- of window (undervoltage OR
overvoltage) conditions. The inputs to these Supply Fault
Detectors are via the VH pin (High Voltage), VBn pins
(positive OR negative) and VPn pins (Positive only) pins
respectively. Either the VH supply or one of the VPn
supplies is used to power the ADM1060 (whichever is
highest). This ensures that, in the event of a supply
failure, the ADM1060 is kept alive for as long as
possible, thus enabling a reliable fault flag to be asserted
and the system to be powered down in an ordered fashion.
Other inputs to the ADM1060 include a Watchdog
Detector (WDI) and 4 General Purpose Inputs (GPIn).
The Watchdog Detector can be used to monitor a
processor clock. If the clock does not toggle (transition
from low to high or from high to low) within a
programmable timeout period (up to 18 sec.), a fail flag
will assert. The 4 General Purpose inputs can be
configured as logic buffers or to detect positive/negative
edges and to generate a logic pulse or level from those
edges. Thus, the user can input control signals from other
parts of their system (eg RESET or POWER_GOOD) to
gate the sequencing of the supplies supervised by the
ADM1060.
The ADM1060 features 9 Programmable Driver Outputs
(PDO’s). All 9 outputs can be configured to be logic
outputs, which can provide multiple functions for the end
user such as RESET generation, POWER_GOOD status,
enabling of LDO’s, Watchdog Timeout assertion etc.
PDO’s 1- 4 have the added feature of being able to
provide an internally charge pumped high voltage for use
as the gate drive of an external N- Channel FET which
could be placed in the path of one of the supplies being
supervised.
All of the inputs and outputs described above are
controlled by the Programmable Logic Block Array. This
is the logic core of the ADM1060. It is comprised of 9
macrocells, one for each PDO. These macrocells are
essentially just wide AND gates. Any/all of the inputs can
be used as an input to these macrocells. The output of a
macrocell can also be used as an input to any macrocell
other than itself (an input to itself would result in a no-
terminating loop). The PLBA outputs control the PDO’s
of the ADM1060 via delay blocks, where a delay of
between 0 and 500ms can be programmed on the rising
and/or the falling edge of the data. This results in a very
flexible sequencing ability. Thus, for instance, PDO1
can be programmed so that it will not assert until, say,
VP2, VP3 and VP4 supplies are in tolerance, VB1 and VH
APPLICATIONS
Central Office Systems
Servers
Infrastructure Network Boards
High density, multi- voltage system cards
GENERAL DESCRIPTION
The ADM1060 is a programmable supervisory/
sequencing device which offers a single chip solution for
multiple power supply fault detection and sequencing in
communications systems.
In central office, servers and other infrastructure systems,
a common backplane dc supply is reduced to multiple
board supplies using dc/dc converters. These multiple
supplies are used to power different sections of the board
(eg) 3.3V Logic circuits, 5V logic circuits, DSP core and
I/O circuits etc. There is usually a requirement that
certain sections power up before others (eg) a DSP core
to power up before the DSP I/O or vice versa. This is in
order to avoid damage, miscommunication or latch- up.
The ADM1060 facilitates this, providing supply fault
detection and sequencing/combinatorial logic for up to 7
independent supplies. The 7 Supply Fault Detectors
consist of one high voltage detector (up to +14.4V), two
bipolar voltage detectors (up to +6V OR down to -6V)
and 4 positive low voltage detectors (up to +6V). All of
the detectors can be programmed to detect undervoltage,
REV. PrF 1/02
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
 ADM1060
have been in tolerance for 200mS, and PDO7 has already
been asserted. A simple sequencing operation would be to
daisy chain each PLB output into the input of the next
PLB such that PDO9 doesn’t assert until PDO8 asserts,
which in turn doesn’t assert until PDO7 asserts etc.
All of the functional capability described here is
programmable through the industry standard 2 wire bus
(SMBus) provided. Device settings can be written to
EEPROM memory for automatic programming of the
device on power-up. The EEPROM is organised in 512
bytes, half of which are used to program all of the
functions on the ADM1060. The other 256 bytes of
EEPROM are for general purpose system use (eg) date
codes, system ID etc. Read/write access to this is also via
the 2 wire interface. In addition, each output state can be
directly overdriven from the serial interface, allowing a
further level of control (eg) a system controlled soft
powerdown.
PROGRAMMABLE
DELAY BLOCKS
PROGRAMMABLE
DRIVER OUPUTS
PDB1
VCC
PPFI4
SEL
PPFI1
VH
8
+12V/+5V SUPPLY
FAULT DETECTOR
15
PDO1
P
R
O
G
R
A
M
M
A
B
L
E
T
RISE
T
FALL
VP1
9
POSITIVE SUPPLY
FAULT DETECTOR 1
VP2
10
VP3
11
16
PDO2
VP4
12
POSITIVE SUPPLY
FAULT DETECTOR 4
17
PDO3
P
L
B
1
O
U
T
M
A
S
T
E
R
S
M
B
U
S
VB1
13
BIPOLAR SUPPLY
FAULT DETECTOR 1
PDO4
L
O
G
I
C
18
VB2
14
BIPOLAR SUPPLY
FAULT DETECTOR 2
PDO5
D
A
T
A
19
C
L
O
C
K
GPI1
28
27
26
25
24
B
L
O
C
K
20
PDO6
GPI2
GPI3
GPI4
INPUT LOGIC
SIGNAL CONDITION
21
PDO7
WDI
WATCHDOG FAULT
DETECTOR
A
R
R
A
Y
22
PDO8
PDB9
VCC
PPFI4
SEL
PPFI1
GND
23
PDO9
6
VREF
T
RISE
T
FALL
Internal
5.5V supply
PLBOUT[0:9]
VCCP
7
REGULATED
5.5V SUPPLY
CHARGE PUMP
OSC
Data, Address and
Write Enable Buses
to store control
V
DD
ARBITATOR
DEVICE
CONTROLLER
EEPROM
SMBus INTERFACE
5
4
3
2
1
ADM1060 FUNCTIONAL BLOCK DIAGRAM
–2–
REV. PrF 1/02
ADM1060–SPECIFICATIONS
1
(VDD = 2.7V to 5.5V
2
, T
A
= -40
o
C to 85
o
C, unless otherwise noted.)
Parameter
Min
Typ
Max Units
Test Conditions/Comments
POWER SUPPLY
Supply Voltage, 3.3V
MAIN
2.7
3.3
5.5 V
Supply Current, I
CC
TBD
2
TBD mA
SUPPLY FAULT DETECTORS
VH Input
Threshold Ranges
Mid Range
2
6
V
Programming Step Size
15.6
mV
High Range
4.8
14.4 V
Programming Step Size
37.5
mV
VPn Inputs
Threshold Ranges
Low Range
1
3
V
Programming Step Size
7.8
mV
Mid Range
2
6
V
Programming Step Size
15.6
mV
VBn Inputs
Threshold Ranges
Negative: Mid Range
-6
-2
V
Programming Step Size
15.6
mV
Positive:
Low Range
1
3
V
Programming Step Size
7.8
mV
Mid Range
2
6
V
Programming Step Size
15.6
mV
Absolute Accuracy
2.5 %
Threshold Programming Resolution
8
Bits
DIGITAL INPUTS
(GPI 1-4,WDI,A0,A1)
Input High Voltage, V
IH
2.0
V
V
DD
=2.7V to 5.5V
Input Low Voltage, V
IL
0.8 V
V
DD
=2.7V to 5.5V
Input High Current, I
IH
-1
A
IN
= V
DD
Input Low Current, I
IL
1
A
IN
= 0
Input Capacitance
TBD
p F
PROGRAMMABLE DRIVER
OUTPUTS
High Voltage (Charge Pump) Mode
(PDO’s 1 to 4)
V
OUT
TBD
14
TBD V
I
OUT
=0
10
V
I
OUT
=2uA
R
PULLUP-
Open Collector Mode
20
k
Switched (fast) Mode
10
V
OL
0.8 V
I
SINK
=TBD
SERIAL BUS DIGITAL INPUTS
(SDA,SCL)
Input High Voltage, V
IH
2.0
V
Input Low Voltage, V
IL
0.8 V
Output Low Voltage, V
OL
0.4 V
I
OUT
= -3.0mA
NOTES
1
These are target specifications and subject to change.
2
At least one supply connected to VH or VPn must be >=3.0V
3
Logic inputs will accept input high voltages up to 5V even when device is operating at supply voltages below 5V.
4
Timing specifications are tested at logic levels of V
IL
= 0.8V for a falling edge and V
IH
= 2.2V for a rising edge.
REV.PrF 1/02
–3–
ADM1060–SPECIFICATIONS (PROPRIETARY INFORMATION)
Parameter
Min
Typ
Max Units
Test Conditions/Comments
SERIAL BUS TIMING
Clock Frequency, f
SCLK
400 KHz See Figure 8c
Glitch Immunity, t
SW
50
ns
See Figure 8c
Bus Free Time, t
BUF
4.7
µs
See Figure 8c
Start Setup Time, t
SU;STA
4.7
µs
See Figure 8c
Start Hold Time, t
HD;STA
4
µs
See Figure 8c
SCL Low Time, t
LOW
4.7
µs
See Figure 8c
SCL High Time, t
HIGH
4
µs
See Figure 8c
SCL, SDA Rise Time, t
r
1000 ns
See Figure 8c
SCL, SDA Fall Time, t
f
300 µs
See Figure 8c
Data Setup Time, t
SU;DAT
250
ns
See Figure 8c
Data Hold Time, t
HD;DAT
300
ns
See Figure 8c
NOTES
1
These are target specifications and subject to change.
2
At least one supply connected to VH or VPn must be >=3.0V
3
Logic inputs will accept input high voltages up to 5V even when device is operating at supply voltages below 5V.
4
Timing specifications are tested at logic levels of V
IL
= 0.8V for a falling edge and V
IH
= 2.2V for a rising edge.
–4–
REV.PrF 1/02
(VDD = 2.7V to 5.5V
2
, T
A
= -40
o
C to 85
o
C, unless otherwise noted.)
ADM1060 (PROPRIETARY INFORMATION)
PIN FUNCTION DESCRIPTION
Pin
Mnemonic
Function
1
A0
Logic input. Controls the 7th bit (LSB) of the 7 bit Serial Bus Address.
2
A1
Logic input. Controls the 6th bit of the 7 bit Serial Bus Address.
3
SDA
Serial Bus data I/O pin. Open- Drain output. Requires 2.2k pullup resistor
4
S C L
Open- Drain Serial Bus Clock pin. Requires 2.2k pullup resistor
5
VDDCAP
V
DD
bypass capacitor pin. A capacitor from this pin to GND stabilises the V
DD
Arbitrator.
0.1
F is recommended for this function.
6
G N D
Ground. Connect to common of power supplies.
7
VCCP
Reservoir Capacitor for Central Charge Pump. This charge pump powers all of the internal
circuits of the ADM1060 and provides the first stage in the tripler circuits used to produce
12V of gate drive on PDO’s 1- 4.
8
V H
High Voltage Supply Input. 2 input ranges. A supply of between 2V and 6V or between
4.8V and 14.4V can be applied to this pin. The V
DD
arbitrator will select this supply to power
the ADM1060 if it is the highest supply supervised.
9-12
VP1-4
Positive Only Supply Inputs. 2 input ranges. A supply of between 1V and 3V or between
2V and 6V can be applied to this pin. The V
DD
arbitrator will select one of these supplies to
power the ADM1060 if it is the highest supply supervised.
13-14 VB1-2
Bipolar Supply Inputs. 2 modes. 2 input ranges in positive mode. 1 input range in negative
mode. A supply of between -6V and -2V can be applied to this pin when set in negative mode.
A supply of between 1V and 3V or between 2V and 6V can be applied to this pin when set in
positive mode.
15-23 PDO_1-9
Programmable Driver Output pin. All 9 can be programmed as logic outputs with multiple
pull-up options to VDD or VPn. PDO’s 1 to 4 can also provide a charge-pump generated
gate drive for external N- Channel FET
24
W D I
Watchdog Input. Used to monitor a processor clock and asserts a fault condition if the clock
fails to transition from low-to-high or high-to-low within a programmed timeout period (up to
18sec).
25-28 GPI_4-1
General Purpose Logic Input. TTL compatible Logic. Can be used as, say, a Manual Reset,
a Chip Enable pin or as an input for a control logic signal which may be critical to the power
up/down sequence of the supplies under control.
ABSOLUTE MAXIMUM RATINGS*
Voltage on VH Pin . . . . . . . . . . . . . . . . . . . . . . . . . . +17 V
Voltage on VP
Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V
Voltage on VB
Pins . . . . . . . . . . . . . . . . . . . . . -7 V to +7V
Voltage on A1,A2 . . . . . . . . . . . . . . . -0.3V to (V
CC
+0.3V)
Voltage on Any Other Input . . . . . . . . . . . . . . -0.3V to 6.5V
Input Current at any pin . . . . . . . . . . . . . . . . . . . . . . ±5mA
Package Input Current . . . . . . . . . . . . . . . . . . . . . . ±20mA
Maximum Junction Temperature (T
J
max) . . . . . . .150 °C
Storage Temperature Range . . . . . . . . . –65°C to +150°C
Lead Temperature, Soldering
Vapor Phase 60 sec . . . . . . . . . . . . . . . . . . . . . . . +215°C
ESD Rating all pins . . . . . . . . . . . . . . . . . . . . . . . . 2000 V
A0
1
28
GPI1
A1
2
27
GPI2
GPI3
SDA
3
26
SCL
4
25
GPI4
ADM1060
VDDCAP
5
24
WDI
GND
6
23
PDO9
VCCP
7
22
PDO8
VH
VP1
8
21
PDO7
9
20
PDO6
PDO5
VP2
10
19
VP3
11
18
PDO4
VP4
12
17
PDO3
VB1
13
16
PDO2
VB2
14
15
PDO1
*Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions above those indicated in the operational section of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
THERMAL CHARACTERISTICS
28-Pin TSSOP Package:
JA
= 98°C/Watt
ADM1060 PIN CONFIGURATION
ORDERING GUIDE
Temperature
Package
Package
Model
Range
Description
Option
ADM1060ARU -40°C to +85°C
28-PinTSSOP
RU-28
REV. PrF 1/02
–5–
[ Pobierz całość w formacie PDF ]