ADMCF341 prb

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PRELIMINARY TECHNICAL DATA
a
DashDSP
TM
28-Lead Flash Mixed-Signal DSP
with Enhanced Analog Front End
Preliminary Technical Data
ADMCF341
TARGET APPLICATIONS
Refrigerator and Air Conditioner Compressors, Washing
Machines, Industrial Variable Speed Drives, HVAC
Programmable 16-Bit Internal Timer with Prescaler
Two Double Buffered Serial Ports with SPI Mode Support
Integrated Power-On Reset Function
Three-Phase 16-Bit PWM Generation Unit
16-Bit Center-Based PWM Generator
Programmable PWM Pulsewidth
Edge Resolution to 50 ns
153 Hz Minimum Switching Frequency
Double/Single Duty Cycle Update Mode Control
Individual Enable and Disable for Each PWM Output
High-Frequency Chopping Mode for Transformer
Coupled Gate Drives
External PWMTRIP Pin
Integrated 6-Channel ADC Subsystem
Three Bipolar I
SENSE
Inputs with Programmable Sample
and Hold Amplifier and Overcurrent Protection (Usable
as Three Dedicated Analog Inputs)
Muxed Auxiliary Analog Inputs
Internal Voltage Reference (2.5 V)
Acquisition Synchronized to PWM Switching Frequency
9-Pin Digital I/O Port
Bit Configurable as Input or Output
Change of State Interrupt Support
Two 16-Bit Auxiliary PWM Timers
Synthesized Analog Output
Programmable Frequency
0% to 100% Duty Cycle
Two Programmable Operational Modes
Independent Mode/Offset Mode
MOTOR TYPES
Permanent Magnet Synchronous Motors (PMSM), Brush-
less DC Motors (BDCM), AC Induction Motors (ACIM)
FEATURES
20 MHz Fixed-Point DSP Core
Single-Cycle Instruction Execution (50 ns)
ADSP-21xx Family Code Compatibility
Independent Computational Units
ALU
Multiplier/Accumulator
Barrel Shifter
Multifunction Instructions
Single-Cycle Context Switch
Powerful Program Sequencer
Zero Overhead Looping
Conditional Instruction Execution
Two Independent Data Address Generators
Memory Configuration
512
16-Bit Data Memory RAM
512
24-Bit Program Memory RAM
4 K
24-Bit Program Memory ROM
24-Bit Program Flash Memory
Three Independent Flash Memory Sectors
3584
24-Bit
Low-Cost Pin-Compatible ROM Option
16-Bit Watchdog Timer
24-Bit, 256
24-Bit, 256
FUNCTIONAL BLOCK DIAGRAM
MOTOR CONTROL PERIPHERALS
MEMORY BLOCK
ADSP-21xx BASE
ARCHITECTURE
DATA
ADDRESS
GENERATORS
DAG 1 DAG 2
ADC SUBSYSTEM
3
PROGRAM
ROM
4K x 24
PROGRAM
FLASH
4K x 24
3
I
SENSE
AMP
AND TRIP
PROGRAM
RAM
512 x 24
DATA
MEMORY
512 x 16
V
REF
ANALOG
INPUTS
6
PROGRAM
SEQUENCER
2.5V
16-BIT
THREE-
PHASE
PWM
SHA
PROGRAM MEMORY ADDRESS
TIMERS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
ARITHMETIC UNITS
SHIFTER
MAC
POR
TIMER
SERIAL PORT
SPORT 0
PIO
2 x 16-BIT
AUX
PWM
WATCH-
DOG
TIMER
SPORT 1
9
2
DashDSP is a trademark of Analog Devices, Inc.
7
REV. PrB
MULTIPLEXED ON EXTERNAL PINS
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
4 K
ALU
 PRELIMINARY TECHNICAL DATA
ADMCF341–SPECIFICATIONS
(V
DD
= 5 V
5%, GND = 0 V, T
A
= –40
C to +85
C, CLKIN = 10 MHz,
unless otherwise noted)
ANALOG-TO-DIGITAL CONVERTER
Parameter
Min
Typ
Max
Unit
Conditions/Comments
Signal Input
0.3
3.5
V
VAUX0, VAUX1, VAUX2
–400
+400
mV
I
SENSE
1, I
SENSE
2, I
SENSE
3
Resolution
1
12
Bits
Linearity Error
2
2
4
Bits
Zero Offset
2
–15
+15
mV
Channel-to-Channel Comparator Match
2
–20
+20
mV
Comparator Delay
600
ns
ADC High Level Input Current
2
10
µA
V
IN
= 3.5 V
ADC Low Level Input Current
2
–10
µA
V
IN
= 0.0 V
NOTES
1
Resolution varies with PWM switching frequency (double update mode) 78.1 kHz = 8 bits, 4.9 kHz = 12 bits.
2
2.44 kHz sample frequency, V1, V2, VAUX0, VAUX1, VAUX2.
Specifications subject to change without notice.
I
SENSE
AMPLIFIER–TRIP
Parameter
Min
Typ
Max
Unit
Conditions/Comments
I
SENSE
Signal Operating Range
–400
+400
mV
I
SENSE
Input Range
–800
+800
mV
I
SENSE
Gain
–2.39 –2.5
–2.59
%
V
IN
= –400 mV to +400 mV
I
SENSE
Gain Channel Matching
3
%
V
IN
= –400 mV to +400 mV
I
SENSE
Gain Stability
1
0.4
%
V
IN
= –400 mV to +400 mV
I
SENSE
Linearity
2
8
9
Bits
I
SENSE
Internal Offset Voltage
2
1.66
1.8
2.1
V
I
SENSE
Internal Offset Stability
3
10
%
0.35% Over Temperature
I
SENSE
Total Harmonic Distortion
3
–40
dB
I
SENSE
Input Current
–120
+10
µA
V
IN
= –400 mV to +400 mV
I
SENSE
Input Resistance
11.5
kΩ
Trip Threshold Low
–650 -500
–450
mV
Trip Threshold High
+450 +500 +650
mV
Trip Minimum Pulsewidth
4
4
5
6
µs
NOTES
1
Variation of gain with V
DD
and temperature.
2
V
IN
= –400 mV to +400 mV.
3
f
IN
= 1 kHz sine wave, V
IN
= –400 mV to +400 mV, f
S
= 4 kHz.
4
High or low trip threshold.
Specifications subject to change without notice.
REV. PrB
–2–
PRELIMINARY TECHNICAL DATA
ADMCF341
ELECTRICAL CHARACTERISTICS
Parameter
Min
Typ
Max
Unit
Conditions/Comments
V
IL
Low Level Input Voltage
0.8
V
V
IH
High Level Input Voltage
2
V
V
OL
Low Level Output Voltage
1
0.4
V
V
OL
Low Level Output Voltage
2
0.8
V
V
OH
High Level Output Voltage
4
V
I
IL
Low Level Input Current
3
–120
µA
I
IL
Low Level Input Current
–10
µA
I
IH
High Level Input Current
4
90
µA
I
IH
High Level Input Current
10
µA
I
OZH
High Level Three-State Leakage Current
5
90
µA
I
OZL
Low Level Three-State Leakage Current
6
–10
µ
A
I
IL
Low Level
PWMTRIP
Current
–10
µ
A
I
DD
Supply Current (Idle)
32
mA
I
DD
Supply Current (Dynamic)
55
mA
NOTES for Electrical Characteristics
1
Output Pins PORTA0–PORTA8, AH, AL, BH, BL, CH, CL.
2
XTAL Pin.
3
Internal Pull-Up,
RESET
.
4
Internal Pull-Down,
PWMTRIP
, PORTA0–PORTA8.
5
Three stateable pins DT1, RFS1, TFS1, SCLK1.
6
Outputs not Switching.
Specifications subject to change without notice.
CURRENT SOURCE
1
Parameter
Min
Typ
Max
Unit
Conditions/Comments
Programming Resolution
3
Bits
Default Current
2
70
83
95
µA
ICONST_TRIM = 0x00
Tuned Current
95
100
105
µA
NOTES
1
For ADC Calibration.
2
0.3 V to 3.5 V ICONST Voltage.
Specifications subject to change without notice.
VOLTAGE REFERENCE
Parameter
Min
Typ
Max
Unit
Conditions/Comments
Voltage Level (V
REF
)
2.40
2.50
2.60
V
Output Voltage Drift
35
ppm/°C
A
= 25°C to 85°C
Specifications subject to change without notice.
POWER-ON RESET
Parameter
Min
Typ
Max
Unit
Conditions/Comments
Reset Threshold
3.2
3.7
4.2
V
Hysteresis
100
mV
Reset Active Timeout Period
3.2
ms
Specifications subject to change without notice.
REV. PrB
–3–
PRELIMINARY TECHNICAL DATA
ADMCF341–SPECIFICATIONS
FLASH MEMORY
Parameter
Min
Typ
Max
Unit
Conditions/Comments
Endurance
10,000
Cycles
Cycle = Erase/Program/Verify
Data Retention
15
Years
Program and Erase Operating Temperature
0
85
°C
Read Operating Temperature
–40
+85
C
Specifications subject to change without notice.
TIMING PARAMETERS
Parameter
Min
Max
Unit
Clock Signals
Signal t
CK
is defined as 0.5 t
CKIN
. The ADMCF341 uses an input clock with a
frequency equal to half the instruction rate; a 10 MHz input clock (which is
equivalent to 100 ns) yields a 50 ns processor cycle (equivalent to 20 MHz). When
t
CK
values are within the range of 0.5 t
CKIN
period, they should be substituted for
all relevant timing parameters to obtain specification value.
Example: t
CKH
= 0.5 t
CK
– 10 ns = 0.5 (50 ns) – 10 ns = 15 ns.
Timing Requirements:
t
CKIN
CLKIN Period
100
150
ns
t
CKIL
CLKIN Width Low
20
ns
t
CKIH
CLKIN Width High
20
ns
Switching Characteristics:
t
CKL
CLKOUT Width Low
0.5 t
CK
– 10
ns
t
CKH
CLKOUT Width High
0.5 t
CK
– 10
ns
t
CKOH
CLKIN High to CLKOUT High
0
20
ns
Control Signals
Timing Requirement:
t
RSP
RESET
Width Low
5 t
CK
1
ns
PWM Shutdown Signals
Timing Requirement:
t
PWMTPW
PWMTRIP
Width Low
t
CK
ns
NOTES
1
Applies after power-up sequence is complete.
Specifications subject to change without notice.
t
CKIN
t
CKIH
CLKIN
t
CKIL
t
CKOH
t
CKH
CLKOUT
t
CKL
Figure 1. Clock Signals
REV. PrB
–4–
°
PRELIMINARY TECHNICAL DATA
TIMING PARAMETERS
ADMCF341
Parameter
Min
Max
Unit
Serial Ports
Timing Requirements:
t
SCK
SCLK Period
100
ns
t
SCS
DR/TFS/RFS Setup before SCLK Low
15
ns
t
SCH
DR/TFS/RFS Hold after SCLK Low
20
ns
t
SCP
SCLK
IN
Width
40
ns
Switching Characteristics
:
t
CC
CLKOUT High to SCLK
OUT
0.25 t
CK
0.25 t
CK
+ 20
ns
t
SCDE
SCLK High to DT Enable
0
ns
t
SCDV
SCLK High to DT Valid
30
ns
t
RH
TFS/RFS
OUT
Hold after SCLK High
0
ns
t
RD
TFS/RFS
OUT
Delay from SCLK High
30
ns
t
SCDH
DT Hold after SCLK High
0
ns
t
SCDD
SCLK High to DT Disable
30
ns
t
TDE
TFS (Alt) to DT Enable
0
ns
t
TDV
TFS (Alt) to DT Valid
25
ns
t
RDV
RFS (Multichannel, Frame Delay Zero) to DT Valid
30
ns
Specifications subject to change without notice.
CLKOUT
t
CC
t
CC
t
SCK
SCLK
t
SCS
t
SCH
t
SCP
t
SCP
DR
RFS
IN
TFS
IN
t
RD
t
RH
RFS
OUT
TFS
OUT
t
SCDV
t
SCDD
t
SCDE
t
SCDH
DT
t
TDE
t
TDV
TFS
(ALTERNATE
FRAME MODE)
t
RDV
RFS
(MULTICHANNEL MODE,
FRAME DELAY 0 [MFD = 0])
Figure 2. Serial Port Timing
REV. PrB
–5–
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